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Reverted gds/sp to reprevious widths.
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@@ -6,8 +6,8 @@ MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
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MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
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MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
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MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
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MM1 Q Q_bar gnd gnd NMOS_VTG W=270.0n L=50n m=1
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MM0 Q_bar Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
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MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
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MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
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.ENDS
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+2
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@@ -6,9 +6,8 @@ MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
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MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
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MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
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MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
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MM1 Q vdd gnd gnd NMOS_VTG W=270.0n L=50n m=1
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MM0 vdd Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
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MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
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MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
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.ENDS
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