catch where strap size is zero

2026-09-01 02:28:31 +02:00 · 2021-06-18 15:24:24 -07:00
parent 8346ad736e
commit 0008df0204
1 changed files with 2 additions and 0 deletions
@@ -39,6 +39,8 @@ class port_data(design.design):
            if(cell_properties.use_strap == True and OPTS.num_ports == 1):
                strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version)
                precharge_width = bitcell.width + strap.width
+            else:
+                precharge_width = bitcell.width
            self.bit_offsets = []
            for i in range(self.num_cols + self.num_spare_cols):
                self.bit_offsets.append(i * precharge_width)