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OpenRAM/compiler/tests/04_pbitcell_test.py

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Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
#!/usr/bin/env python2.7
"""
The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell
2018-02-28 20:14:53 +01:00
Run regresion tests on a parameterized bitcell
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
"""
import unittest
The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell
2018-02-28 20:14:53 +01:00
from testutils import header,openram_test
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell
2018-02-28 20:14:53 +01:00
from globals import OPTS
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
import debug
OPTS = globals.OPTS
#@unittest.skip("SKIPPING 04_pbitcell_test")
The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell
2018-02-28 20:14:53 +01:00
class pbitcell_test(openram_test):
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell
2018-02-28 20:14:53 +01:00
global verify
import verify
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
OPTS.check_lvsdrc = False
import pbitcell
import tech
adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports.
2018-05-10 18:38:02 +02:00
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=2)
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
self.local_check(tx)
adding unit test for bitcell array using pbitcell
2018-03-07 01:36:11 +01:00
adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports.
2018-05-10 18:38:02 +02:00
debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell.pbitcell(num_readwrite=0,num_write=2,num_read=2)
self.local_check(tx)
debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=2)
self.local_check(tx)
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=0)
adding unit test for bitcell array using pbitcell
2018-03-07 01:36:11 +01:00
self.local_check(tx)
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
OPTS.check_lvsdrc = True
The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell
2018-02-28 20:14:53 +01:00
globals.end_openram()
Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.
2018-01-09 22:39:42 +01:00
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()