mirror of https://github.com/VLSIDA/OpenRAM.git
60 lines
1.8 KiB
Python
60 lines
1.8 KiB
Python
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#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class worst_case_timing_sram_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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OPTS.trim_netlist = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import worst_case
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=1
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debug.info(1, "Testing the timing for 2 bits inside a 2bit, 16words SRAM with 1 bank")
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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wc = worst_case(s.s, tempspice, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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probe_address = "1" * s.s.addr_size
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probe_data = s.s.word_size - 1
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wc.analyze(probe_address, probe_data, slews, loads)
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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