mirror of https://github.com/VLSIDA/OpenRAM.git
56 lines
2.2 KiB
Python
56 lines
2.2 KiB
Python
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import hierarchy_design
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import contact
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import globals
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import verify
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import debug
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import os
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from globals import OPTS
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class design(hierarchy_design.hierarchy_design):
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"""
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This is the same as the hierarchy_design class except it contains
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some DRC constants and analytical models for other modules to reuse.
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"""
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def __init__(self, name):
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hierarchy_design.hierarchy_design.__init__(self,name)
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self.setup_drc_constants()
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self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
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self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space)
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# SCMOS doesn't have m4...
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#self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
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self.m3_pitch = self.m2_pitch
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def setup_drc_constants(self):
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""" These are some DRC constants used in many places in the compiler."""
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from tech import drc
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self.well_width = drc["minwidth_well"]
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self.poly_width = drc["minwidth_poly"]
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self.poly_space = drc["poly_to_poly"]
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self.m1_width = drc["minwidth_metal1"]
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self.m1_space = drc["metal1_to_metal1"]
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self.m2_width = drc["minwidth_metal2"]
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self.m2_space = drc["metal2_to_metal2"]
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self.m3_width = drc["minwidth_metal3"]
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self.m3_space = drc["metal3_to_metal3"]
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self.active_width = drc["minwidth_active"]
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self.contact_width = drc["minwidth_contact"]
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self.poly_to_active = drc["poly_to_active"]
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self.poly_extend_active = drc["poly_extend_active"]
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self.contact_to_gate = drc["contact_to_gate"]
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self.well_enclose_active = drc["well_enclosure_active"]
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self.implant_enclose_active = drc["implant_enclosure_active"]
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self.implant_space = drc["implant_to_implant"]
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def analytical_power(self, proc, vdd, temp, load):
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""" Get total power of a module """
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total_module_power = self.return_power()
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for inst in self.insts:
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total_module_power += inst.mod.analytical_power(proc, vdd, temp, load)
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return total_module_power
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