2022-10-05 07:16:12 +02:00
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### [Go Back](./index.md#directory)
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2022-10-05 06:58:49 +02:00
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# Library Cells
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This page of the documentation explains the library cells of OpenRAM.
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## Table of Contents
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1. [Required Hard/Custom Cells](#required-hardcustom-cells)
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2. [Bitcell(s)](#bitcells)
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3. [Multiport Bitcells](#multiport-bitcells)
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4. [Parameterized Bitcell](#parameterized-bitcell)
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5. [Sense Amplifier](#sense-amplifier)
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6. [DFF](#dff)
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7. [Tristate/Write Driver](#tristatewrite-driver)
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## Required Hard/Custom Cells
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* Located in
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* `$OPENRAM_TECH/<tech>/gds_lib`
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* `$OPENRAM_TECH/<tech>/sp_lib`
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* A few library cells with layout and SPICE:
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* Bitcell (and dummy and replica bitcell)
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* Sense amplifier
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* DFF (from a standard cell library)
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* (Removing soon: write driver, tristate)
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* P&R border layer defined for placement
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* Sense amplifier pitch matched width to bitcell
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## Bitcell(s)
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* Python code is in `$OPENRAM_HOME/bitcells`
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* Layout in `$OPENRAM_TECH/<tech>/gds_lib `
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* SPICE in `$OPENRAM_TECH/<tech>/sp_lib`
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* Can be a foundry bitcell if you have the GDS and SPICE.
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* May include multiple port configurations:
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* `bitcell.py` uses `cell_6t.{gds,sp}` - standard 1rw port
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* `bitcell_1w_1r.py` uses `cell_1w_1r.{gds,sp}` for 1w and 1r port
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* `bitcell_1rw_1r.py` uses `cell_1rw_1r.{gds,sp}` for 1rw and 1r port
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* Wish list: pin names are fixed right now as `bl`, `br`, `wl`, `vdd`, `gnd`
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## Multiport Bitcells
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* Based on 6T SRAM cell
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* Standard read-write
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* Isolated read-only ports
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* Write-only port (not sized for reads)
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* Can accommodate foundry bitcells
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## Parameterized Bitcell
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* If a custom bitcell is not available, we create one with user design rules.
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* Not good for area, but may still be better than DFFs.
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* Can be useful for simulation/functional work before custom bitcell is available.
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* Example 1 RW pbitcell compared to custom 1RW
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<img height="300" src="../assets/images/bitcells/parameterized_1.png">
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<img height="300" src="../assets/images/bitcells/parameterized_2.png">
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## Sense Amplifier
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* Needs a sense amplifier that is pitch matched to the bitcell.
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* `$OPENRAM_TECH/gds_lib/sense_amp.gds`
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* `$OPENRAM_TECH/sp_lib/sense_amp.sp`
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* `$OPENRAM_HOME/modules/sense_amp.py`
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* Wish list: pin names are fixed right now as `bl`, `br`, `dout`, `en`, `vdd`, `gnd`
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## DFF
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* Needs a standard cell DFF for the address and data registers.
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* `$OPENRAM_TECH/gds_lib/dff.gds `
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* `$OPENRAM_TECH/sp_lib/dff.sp`
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* `$OPENRAM_HOME/modules/dff.py`
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* Have auxiliary code to create:
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* Buffered DFFs (`dff_buf.py`) using dynamically generated inverters (pinv)
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* Inverted output DFFs (`dff_inv.py`) using a dynamically generated inverters (pinv)
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* 2-D DFF arrays
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* Regular DFF arrays (`dff_array.py`)
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* Buffered DFF arrays (`dff_buf_array.py`)
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* Inverted DFF array (`dff_inv_array.py`)
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* Wish list: pin names are fixed right now as `D`, `Q`, `Qb`, `clk`, `vdd`, `gnd`
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## Tristate/Write Driver
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* Tristate is used for multi-bank implementations
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* Write driver drives the data onto the bitlines
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* Both of these are currently library cells, but plans are to make them dynamically generated (`ptristate.py` and `pwrite_driver.py`)
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