mirror of https://github.com/VLSIDA/OpenRAM.git
117 lines
2.4 KiB
Makefile
117 lines
2.4 KiB
Makefile
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CUR_DIR = $(shell pwd)
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TEST_DIR = ${CUR_DIR}/tests
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MAKEFLAGS += -j 2
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# Library test
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LIBRARY_TESTS = \
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01_library_drc_test.py \
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02_library_lvs_test.py
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# Technology and DRC tests (along with ptx)
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TECH_TESTS = \
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03_contact_test.py \
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03_ptx_1finger_pmos_test.py \
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03_ptx_4finger_nmos_test.py \
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03_path_test.py \
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03_ptx_3finger_nmos_test.py \
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03_ptx_4finger_pmos_test.py \
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03_ptx_1finger_nmos_test.py \
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03_ptx_3finger_pmos_test.py \
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03_wire_test.py
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# Parameterized cells
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PCELLS_TESTS = \
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04_pinv_1x_test.py \
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04_pinv_1x_beta_test.py \
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04_pinv_2x_test.py \
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04_pinv_10x_test.py \
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04_pnand2_test.py \
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04_pnor2_test.py \
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04_pnand3_test.py\
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04_wordline_driver_test.py \
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04_precharge_test.py
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# Dynamically generated modules and arrays
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MODULE_TESTS = \
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05_bitcell_array_test.py \
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06_hierarchical_decoder_test.py \
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06_hierarchical_predecode2x4_test.py \
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06_hierarchical_predecode3x8_test.py \
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07_single_level_column_mux_array_test.py \
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08_precharge_array_test.py \
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09_sense_amp_array_test.py \
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10_write_driver_array_test.py \
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11_ms_flop_array_test.py \
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12_tri_gate_array_test.py \
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13_delay_chain_test.py \
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14_replica_bitline_test.py \
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16_control_logic_test.py
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# Top-level SRAM configurations
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TOP_TESTS = \
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19_multi_bank_test.py \
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19_single_bank_test.py \
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20_sram_1bank_test.py \
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20_sram_2bank_test.py \
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20_sram_4bank_test.py
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# All simulation tests.
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CHAR_TESTS = \
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21_hspice_delay_test.py \
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21_ngspice_delay_test.py \
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21_ngspice_setuphold_test.py \
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21_hspice_setuphold_test.py \
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22_sram_func_test.py \
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22_pex_func_test_with_pinv.py \
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23_lib_sram_prune_test.py \
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23_lib_sram_test.py
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# Keep the model lib test here since it is fast
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# and doesn't need simulation.
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USAGE_TESTS = \
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23_lib_sram_model_test.py \
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24_lef_sram_test.py \
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25_verilog_sram_test.py
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ALL_FILES = \
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${LIBRARY_TESTS} \
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${TECH_TESTS} \
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${PCELLS_TESTS} \
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${MODULES_TESTS} \
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${TOP_TESTS} \
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${CHAR_TESTS} \
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${USAGE_TESTS}
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default all:
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$(ALL_FILES):
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python ${TEST_DIR}/$@ -t freepdk45
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python ${TEST_DIR}/$@ -t scn3me_subm
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# Library tests
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lib: ${LIBRARY_TESTS}
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# Transistor and wire tests
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tech: ${TECH_TESTS}
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# Dynamically generated cells
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pcells: ${PCELLS_TESTS}
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# Dynamically generated modules
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modules: ${MODULES_TESTS}
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# Top level SRAM tests
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top: ${TOP_TESTS}
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# Timing and characterization tests
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char: ${CHAR_TESTS}
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# Usage and file generation
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usage: ${USAGE_TESTS}
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clean:
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find . -name \*.pyc -exec rm {} \;
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find . -name \*~ -exec rm {} \;
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