2022-10-15 03:27:39 +02:00
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### [Go Back](./index.md#table-of-contents)
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2022-10-05 06:58:49 +02:00
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# Architecture
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This page of the documentation explains the architecture of OpenRAM.
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## Table of Contents
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1. [SRAM Architecture](#sram-architecture)
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## SRAM Architecture
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* Bit-cell Array
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* Multiport Bitcells
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* Each port:
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* Address Decoder(s)
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* Wordline Driver(s)
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* Column Multiplexer(s)
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* Bitline Precharge(s)
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* Sense Amplifier(s)
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* Write Driver(s)
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* Control Logic with Replica Bitline
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2023-04-20 08:32:06 +02:00
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## ROM Architecture
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* Bit-cell Array
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* 1T NAND Bitcell
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* Row Address Decoder
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* Wordline Driver(s)
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* Column Multiplexer
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* Column Pre-Decoder
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* Bitline Precharge(s)
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* Control Logic
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