mirror of https://github.com/VLSIDA/OpenRAM.git
73 lines
2.3 KiB
Python
73 lines
2.3 KiB
Python
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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# @unittest.skip("SKIPPING psram_wmask_func_test")
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class psram_wmask_func_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.bitcell = "bitcell_1w_1r"
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OPTS.replica_bitcell = "replica_bitcell_1w_1r"
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OPTS.num_rw_ports = 0
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OPTS.num_w_ports = 1
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OPTS.num_r_ports = 1
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import functional, delay
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from sram_config import sram_config
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c = sram_config(word_size=8,
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num_words=16,
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write_size=2,
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num_banks=1)
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c.words_per_row = 1
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c.recompute_sizes()
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debug.info(1,
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"Functional test for sram with {} bit words, {} words, {} words per row, {} bit writes, {} banks".format(
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.write_size,
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c.num_banks))
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s = factory.create(module_type="sram", sram_config=c)
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f.num_cycles = 10
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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