2016-11-08 18:57:35 +01:00
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2018-02-02 23:08:56 +01:00
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.SUBCKT sense_amp bl br dout en vdd gnd
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2016-11-08 18:57:35 +01:00
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M_1 dout net_1 vdd vdd pmos_vtg w=540.0n l=50.0n
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M_3 net_1 dout vdd vdd pmos_vtg w=540.0n l=50.0n
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M_2 dout net_1 net_2 gnd nmos_vtg w=270.0n l=50.0n
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M_8 net_1 dout net_2 gnd nmos_vtg w=270.0n l=50.0n
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2018-02-02 23:08:56 +01:00
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M_5 bl en dout vdd pmos_vtg w=720.0n l=50.0n
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M_6 br en net_1 vdd pmos_vtg w=720.0n l=50.0n
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M_7 net_2 en gnd gnd nmos_vtg w=270.0n l=50.0n
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2016-11-08 18:57:35 +01:00
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.ENDS sense_amp
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