mirror of https://github.com/VLSIDA/OpenRAM.git
35 lines
1.1 KiB
Plaintext
35 lines
1.1 KiB
Plaintext
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Develop set of vector/point manipulation functions and replace
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everywhere. (Bin)
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Use signal names from the technology file. Right now they are hard
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coded everywhere. For example: DATA, ADDR, etc.
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Cell name (ms_flop) is hard coded in characterizer, pin names are hard
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coded too. This should come from the config file which dynamically
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loads the module names.
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Autodetect ideal number of threads for hspice.
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vdd and gnd are hard coded in some places. The names should come from
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the tech file.
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Some modules use upper/lower via layer instead of min width DRC rule
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from tech file.
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Fix the size of labels. For some reason, they are HUGE. (Samira)
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Add the clock buffer internal to control logic. Simulation uses
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1-4-8-16 inverters right now. Replace simulation with simple clock
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buffer after fixing.
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Check out the multibank organization in sram.py and bank.py to see if
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it can be reduced or made more readable.
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Move/modify similar functions in hierarchical_predecode2x4 and
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hierarchical_predecode3x8 to hierarchical_predecode class
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Fix stimuli.py to be more readable.
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Add tests for bitcell, ms_flop, replica_bitcell, sens_amp, tri_gate, write_driver?
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