mirror of https://github.com/VLSIDA/OpenRAM.git
341 lines
20 KiB
Python
341 lines
20 KiB
Python
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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from replica_bitcell_array import replica_bitcell_array
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from vector import vector
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from sky130_bitcell_base_array import sky130_bitcell_base_array
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from utils import round_to_grid
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from math import sqrt
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from tech import drc
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from tech import array_row_multiple
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from tech import array_col_multiple
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from globals import OPTS
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class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_array):
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"""
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Creates a bitcell arrow of cols x rows and then adds the replica
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and dummy columns and rows. Replica columns are on the left and
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right, respectively and connected to the given bitcell ports.
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Dummy are the outside columns/rows with WL and BL tied to gnd.
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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self.all_ports = list(range(total_ports))
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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if rbl:
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self.rbl = rbl
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else:
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self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
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# This specifies which RBL to put on the left or right
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# by port number
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# This could be an empty list
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if left_rbl != None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = [0]
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# This could be an empty list
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if right_rbl != None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[1] if len(self.all_ports) > 1 else []
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self.rbls = self.left_rbl + self.right_rbl
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if ((self.column_size + self.rbl[0] + self.rbl[1]) % array_col_multiple != 0):
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debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.column_size + self.rbl[0] + self.rbl[1], array_col_multiple), -1)
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if ((self.row_size + self.rbl[0] + self.rbl[1]) % array_row_multiple != 0):
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debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.row_size + self.rbl[0] + self.rbl[1], array_row_multiple), -15)
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super().__init__(self.row_size, self.column_size, rbl, left_rbl, right_rbl, name)
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def create_layout(self):
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# We will need unused wordlines grounded, so we need to know their layer
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# and create a space on the left and right for the vias to connect to ground
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pin = self.cell.get_pin(self.cell.get_all_wl_names()[0])
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pin_layer = pin.layer
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self.unused_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
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self.unused_offset = vector(self.unused_pitch, 0)
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height)
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self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
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self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
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# Everything is computed with the main array at (self.unused_pitch, 0) to start
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self.bitcell_array_inst.place(offset=self.unused_offset)
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self.add_replica_columns()
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self.add_end_caps()
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# Array was at (0, 0) but move everything so it is at the lower left
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self.offset_all_coordinates()
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# Add extra width on the left and right for the unused WLs
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#self.width = self.dummy_col_insts[0].rx() + self.unused_offset[0]
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self.width = self.dummy_col_insts[1].rx()
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self.height = self.dummy_col_insts[0].uy()
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self.add_layout_pins()
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self.route_unused_wordlines()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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super().add_pins()
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self.add_pin("vpb", "BIAS")
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self.add_pin("vnb", "BIAS")
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def add_replica_columns(self):
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""" Add replica columns on left and right of array """
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# Grow from left to right, toward the array
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for bit, port in enumerate(self.left_rbl):
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offset = self.bitcell_array_inst.ll() \
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- vector(0, self.col_cap_bottom.height) \
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- vector(0, self.dummy_row.height) \
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- vector(self.replica_columns[0].width, 0)
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self.replica_col_insts[bit].place(offset + vector(0, self.replica_col_insts[bit].height), mirror="MX")
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# Grow to the right of the bitcell array, array outward
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for bit, port in enumerate(self.right_rbl):
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offset = self.bitcell_array_inst.lr() \
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+ self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) \
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+ self.strap_offset.scale(bit, -self.rbl[0] - 1)
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self.replica_col_insts[self.rbl[0] + bit].place(offset)
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# Replica dummy rows
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# Add the dummy rows even if we aren't adding the replica column to this bitcell array
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# These grow up, toward the array
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for bit in range(self.rbl[0]):
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dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
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self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
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mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
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# These grow up, away from the array
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for bit in range(self.rbl[1]):
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dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
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self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
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mirror="MX" if bit % 2 else "R0")
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def add_end_caps(self):
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""" Add dummy cells or end caps around the array """
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dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1]) + self.bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=dummy_row_offset)
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dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) + self.unused_offset
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self.dummy_row_insts[0].place(offset=dummy_row_offset + vector(0, self.dummy_row_insts[0].height), mirror="MX")
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# Far left dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) * (1 + self.strap_offset.x / self.cell.width), -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) - vector(self.replica_col_insts[0].width, 0) + self.unused_offset
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self.dummy_col_insts[0].place(offset=dummy_col_offset, mirror="MY")
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# Far right dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) * (1 + self.strap_offset.x / self.cell.width), -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) + self.bitcell_array_inst.lr()
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self.dummy_col_insts[1].place(offset=dummy_col_offset)
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def route_unused_wordlines(self):
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""" Connect the unused RBL and dummy wordlines to gnd """
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return
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# This grounds all the dummy row word lines
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap.get_wordline_names():
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self.ground_pin(inst, wl_name)
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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self.ground_pin(inst, pin_name)
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def add_layout_pins(self):
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""" Add the layout pins """
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for row_end in self.dummy_col_insts:
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row_end = row_end.mod
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for (rba_wl_name, wl_name) in zip(self.get_all_wordline_names(), row_end.get_wordline_names()):
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pin = row_end.get_pin(wl_name)
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self.add_layout_pin(text=rba_wl_name,
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layer=pin.layer,
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offset=vector(0,pin.ll().scale(0, 1)[1]),
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#width=self.width,
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width=pin.width(),
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height=pin.height())
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pin_height = (round_to_grid(drc["minarea_m3"] / round_to_grid(sqrt(drc["minarea_m3"]))) + drc["{0}_to_{0}".format('m3')])
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drc_width = drc["{0}_to_{0}".format('m3')]
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# vdd/gnd are only connected in the perimeter cells
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# replica column should only have a vdd/gnd in the dummy cell on top/bottom
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supply_insts = self.dummy_row_insts + self.replica_col_insts
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for pin_name in self.supplies:
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for supply_inst in supply_insts:
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vdd_alternate = 0
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gnd_alternate = 0
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for cell_inst in supply_inst.mod.insts:
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inst = cell_inst.mod
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for pin in inst.get_pins(pin_name):
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if pin.name == 'vdd':
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if vdd_alternate:
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connection_offset = 0.035
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vdd_alternate = 0
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else:
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connection_offset = -0.035
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vdd_alternate = 1
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connection_width = drc["minwidth_{}".format('m1')]
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track_offset = 1
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elif pin.name == 'gnd':
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if gnd_alternate:
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connection_offset = 0.035
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gnd_alternate = 0
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else:
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connection_offset = -0.035
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gnd_alternate = 1
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connection_width = drc["minwidth_{}".format('m1')]
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track_offset = 4
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pin_width = round_to_grid(sqrt(drc["minarea_m3"]))
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pin_height = round_to_grid(drc["minarea_m3"] / pin_width)
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if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent' or 'corner' in inst.cell_name:
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if 'dummy_row' in supply_inst.name and supply_inst.mirror == 'MX':
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pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
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elif 'dummy_row' in supply_inst.name:
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pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
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elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
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pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
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elif 'replica_col' in supply_inst.name:
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pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer='m2',
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offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
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#self.add_power_pin(name=pin_name,
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# loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0),
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# start_layer=pin.layer,
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# end_layer='m2')
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# add well contacts to perimeter cells
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for pin_name in ['vpb', 'vnb']:
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for supply_inst in supply_insts:
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vnb_alternate = 0
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vpb_alternate = 0
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for cell_inst in supply_inst.mod.insts:
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inst = cell_inst.mod
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for pin in inst.get_pins(pin_name):
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if pin.name == 'vpb':
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if vpb_alternate:
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connection_offset = 0.01
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vpb_alternate = 0
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else:
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connection_offset = 0.02
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vpb_alternate = 1
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connection_width = drc["minwidth_{}".format('m1')]
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track_offset = 2
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elif pin.name == 'vnb':
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if vnb_alternate:
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connection_offset = -0.01
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vnb_alternate = 0
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else:
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connection_offset = -0.02
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vnb_alternate = 1
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connection_width = drc["minwidth_{}".format('m1')]
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track_offset = 3
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if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent':
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if 'dummy_row' in supply_inst.name and supply_inst.mirror == 'MX':
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pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
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elif 'dummy_row' in supply_inst.name:
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pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
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elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
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pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
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self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
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|
|
elif 'replica_col' in supply_inst.name:
|
||
|
|
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||
|
|
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||
|
|
self.add_via_stack_center(from_layer=pin.layer,
|
||
|
|
to_layer='m2',
|
||
|
|
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||
|
|
#self.add_power_pin(name=pin_name,
|
||
|
|
# loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0),
|
||
|
|
# start_layer=pin.layer)
|
||
|
|
|
||
|
|
min_area = drc["minarea_{}".format('m3')]
|
||
|
|
for track,supply, offset in zip(range(1,5),['vdd','vpb','vnb','gnd'],[min_area * 6,min_area * 6, 0, 0]):
|
||
|
|
y_offset = track * (pin_height + drc_width*2)
|
||
|
|
self.add_segment_center('m2', vector(0,-y_offset), vector(self.width, -y_offset), drc["minwidth_{}".format('m2')])
|
||
|
|
self.add_segment_center('m2', vector(0,self.height + y_offset), vector(self.width, self.height + y_offset), drc["minwidth_{}".format('m2')])
|
||
|
|
self.add_power_pin(name=supply,
|
||
|
|
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, -y_offset),
|
||
|
|
start_layer='m2')
|
||
|
|
self.add_power_pin(name=supply,
|
||
|
|
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, self.height + y_offset),
|
||
|
|
start_layer='m2')
|
||
|
|
self.add_power_pin(name=supply,
|
||
|
|
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, -y_offset),
|
||
|
|
start_layer='m2')
|
||
|
|
self.add_power_pin(name=supply,
|
||
|
|
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, self.height + y_offset),
|
||
|
|
start_layer='m2')
|
||
|
|
|
||
|
|
self.offset_all_coordinates()
|
||
|
|
self.height = self.height + self.dummy_col_insts[0].lr().y * 2
|
||
|
|
|
||
|
|
for pin_name in self.all_bitline_names:
|
||
|
|
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||
|
|
for pin in pin_list:
|
||
|
|
if 'bl' in pin.name:
|
||
|
|
self.add_layout_pin(text=pin_name,
|
||
|
|
layer=pin.layer,
|
||
|
|
offset=pin.ll().scale(1, 0),
|
||
|
|
width=pin.width(),
|
||
|
|
height=self.height)
|
||
|
|
elif 'br' in pin_name:
|
||
|
|
self.add_layout_pin(text=pin_name,
|
||
|
|
layer=pin.layer,
|
||
|
|
offset=pin.ll().scale(1, 0) + vector(0,pin_height + drc_width*2),
|
||
|
|
width=pin.width(),
|
||
|
|
height=self.height - 2 *(pin_height + drc_width*2))
|
||
|
|
# Replica bitlines
|
||
|
|
if len(self.rbls) > 0:
|
||
|
|
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||
|
|
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
|
||
|
|
for (bl_name, pin_name) in zip(names, pin_names):
|
||
|
|
pin = inst.get_pin(pin_name)
|
||
|
|
if 'rbl_bl' in bl_name:
|
||
|
|
self.add_layout_pin(text=bl_name,
|
||
|
|
layer=pin.layer,
|
||
|
|
offset=pin.ll().scale(1, 0),
|
||
|
|
width=pin.width(),
|
||
|
|
height=self.height)
|
||
|
|
elif 'rbl_br' in bl_name:
|
||
|
|
self.add_layout_pin(text=bl_name,
|
||
|
|
layer=pin.layer,
|
||
|
|
offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),
|
||
|
|
width=pin.width(),
|
||
|
|
height=self.height - 2 *(pin_height + drc_width*2))
|
||
|
|
return
|