mirror of https://github.com/VLSIDA/OpenRAM.git
47 lines
1.4 KiB
Plaintext
47 lines
1.4 KiB
Plaintext
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# SUE version MMI_SUE5.0.7
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proc SCHEMATIC_cell_6t {} {
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make inout -name BL -origin {190 360}
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make inout -name BR -origin {830 360}
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make input -name WL -origin {240 120}
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make global -orient RXY -name vdd -origin {520 160}
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make global -name gnd -origin {510 600}
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make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
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make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
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make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
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make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
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make nmos -W 2.4u -L 0.6u -origin {630 490}
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make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
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make_wire 630 550 630 530
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make_wire 400 530 400 550
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make_wire 400 190 400 170
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make_wire 630 170 630 190
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make_wire 400 360 400 270
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make_wire 310 360 400 360
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make_wire 630 360 630 450
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make_wire 630 360 700 360
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make_wire 270 300 270 120
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make_wire 270 120 740 120
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make_wire 740 120 740 300
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make_wire 230 360 190 360
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make_wire 780 360 830 360
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make_wire 510 550 400 550
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make_wire 510 550 630 550
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make_wire 510 550 510 600
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make_wire 520 170 400 170
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make_wire 520 170 630 170
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make_wire 520 160 520 170
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make_wire 240 120 270 120
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make_wire 460 290 630 290
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make_wire 460 290 460 490
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make_wire 460 290 460 230
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make_wire 630 290 630 360
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make_wire 630 290 630 270
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make_wire 570 420 400 420
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make_wire 570 420 570 490
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make_wire 570 420 570 230
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make_wire 400 420 400 360
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make_wire 400 420 400 450
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}
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