2016-11-08 18:57:35 +01:00
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.SUBCKT cell_6t bl br wl vdd gnd
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2018-11-05 19:59:08 +01:00
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* Inverter 1
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MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n
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* Inverer 2
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MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n
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* Access transistors
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2018-07-26 20:26:47 +02:00
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MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
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2018-11-05 19:59:08 +01:00
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MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
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2016-11-08 18:57:35 +01:00
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.ENDS cell_6t
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