mirror of https://github.com/VLSIDA/OpenRAM.git
81 lines
2.8 KiB
Python
81 lines
2.8 KiB
Python
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice, parameter
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import logical_effort
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import utils
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import debug
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class inv_dec(design.design):
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"""
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INV for address decoders.
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"""
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pin_names = ["A", "Z", "vdd", "gnd"]
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type_list = ["INPUT", "OUTPUT", "POWER", "GROUND"]
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(width, height) = utils.get_libcell_size("inv_dec",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "inv_dec", GDS["unit"])
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def __init__(self, name="inv_dec", height=None):
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design.design.__init__(self, name)
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self.width = inv_dec.width
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self.height = inv_dec.height
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self.pin_map = inv_dec.pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["inv_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""
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Return the capacitance of the gate connection in generic capacitive
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units relative to the minimum width of a transistor
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"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 1
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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