mirror of https://github.com/VLSIDA/OpenRAM.git
55 lines
1.2 KiB
Python
55 lines
1.2 KiB
Python
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#!/usr/bin/env python2.7
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"Run a regresion test the library cells for DRC"
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import unittest
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from testutils import header
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import sys,os
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sys.path.append(os.path.join(sys.path[0],"../.."))
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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import debug
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import calibre
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import vector
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class no_blockages_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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import router
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#r=router.router("A_to_B_no_blockages.gds")
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r=router.router("A_to_B_m1m2_blockages.gds")
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r.set_layers(("metal1","via1","metal2"))
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r.create_routing_grid()
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r.set_source("A")
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r.set_target("B")
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r.find_blockages()
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r.rg.view()
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#drc_errors = calibre.run_drc(name, gds_name)
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drc_errors = 1
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# fails if there are any DRC errors on any cells
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self.assertEqual(drc_errors, 0)
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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