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OpenRAM/compiler/tests/sp_files/sram_2_16_1_freepdk45.sp

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Added spice files for the command line char
2023-04-20 02:23:00 +02:00
**************************************************
* OpenRAM generated memory.
* Words: 16
* Data bits: 1
* Banks: 1
* Column mux: 1:1
* Trimmed: False
* LVS: False
**************************************************
* spice ptx M{0} {1} pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
* spice ptx M{0} {1} nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01p ad=0.01p
.SUBCKT sram_pinv_3
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01p ad=0.01p
.ENDS sram_pinv_3
* spice ptx M{0} {1} pmos_vtg m=2 w=0.675u l=0.05u pd=1.45u ps=1.45u as=0.08p ad=0.08p
* spice ptx M{0} {1} nmos_vtg m=2 w=0.225u l=0.05u pd=0.55u ps=0.55u as=0.03p ad=0.03p
.SUBCKT sram_pinv_8
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=2 w=0.675u l=0.05u pd=1.45u ps=1.45u as=0.08p ad=0.08p
Mpinv_nmos Z A gnd gnd nmos_vtg m=2 w=0.225u l=0.05u pd=0.55u ps=0.55u as=0.03p ad=0.03p
.ENDS sram_pinv_8
.SUBCKT sram_pinv_5
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01p ad=0.01p
.ENDS sram_pinv_5
.SUBCKT sram_pdriver_1
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* sizes: [1, 5]
Xbuf_inv1
+ A Zb1_int vdd gnd
+ sram_pinv_5
Xbuf_inv2
+ Zb1_int Z vdd gnd
+ sram_pinv_8
.ENDS sram_pdriver_1
* spice ptx M{0} {1} nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
* spice ptx M{0} {1} nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
* spice ptx M{0} {1} pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
.SUBCKT sram_pnand2_0
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pnand2_0
* spice ptx M{0} {1} nmos_vtg m=4 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
* spice ptx M{0} {1} pmos_vtg m=4 w=0.81u l=0.05u pd=1.72u ps=1.72u as=0.10p ad=0.10p
.SUBCKT sram_pinv_2
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=4 w=0.81u l=0.05u pd=1.72u ps=1.72u as=0.10p ad=0.10p
Mpinv_nmos Z A gnd gnd nmos_vtg m=4 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
.ENDS sram_pinv_2
.SUBCKT sram_pdriver
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* sizes: [12]
Xbuf_inv1
+ A Z vdd gnd
+ sram_pinv_2
.ENDS sram_pdriver
.SUBCKT sram_pand2
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Xpand2_nand
+ A B zb_int vdd gnd
+ sram_pnand2_0
Xpand2_inv
+ zb_int Z vdd gnd
+ sram_pdriver
.ENDS sram_pand2
* spice ptx M{0} {1} pmos_vtg m=1 w=0.54u l=0.05u pd=1.18u ps=1.18u as=0.07p ad=0.07p
* spice ptx M{0} {1} nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.SUBCKT sram_pinv_0
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.54u l=0.05u pd=1.18u ps=1.18u as=0.07p ad=0.07p
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pinv_0
* spice ptx M{0} {1} pmos_vtg m=2 w=0.54u l=0.05u pd=1.18u ps=1.18u as=0.07p ad=0.07p
* spice ptx M{0} {1} nmos_vtg m=2 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.SUBCKT sram_pinv_1
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=2 w=0.54u l=0.05u pd=1.18u ps=1.18u as=0.07p ad=0.07p
Mpinv_nmos Z A gnd gnd nmos_vtg m=2 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pinv_1
* File: DFFPOSX1.pex.netlist
* Created: Wed Jan 2 18:36:24 2008
* Program "Calibre xRC"
* Version "v2007.2_34.24"
*
.subckt dff D Q clk vdd gnd
*
MM21 Q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
MM20 gnd Q a_76_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
MM18 a_66_6# clk a_61_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
MM17 a_61_6# a_34_4# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
MM10 gnd clk a_2_6# gnd NMOS_VTG L=5e-08 W=5e-07
MM16 a_34_4# a_22_6# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
MM15 gnd a_34_4# a_31_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
MM14 a_31_6# clk a_22_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
MM13 a_22_6# a_2_6# a_17_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
MM12 a_17_6# D gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
MM11 Q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06
MM9 vdd Q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07
MM8 a_76_84# clk a_66_6# vdd PMOS_VTG L=5e-08 W=2.5e-07
MM7 a_66_6# a_2_6# a_61_74# vdd PMOS_VTG L=5e-08 W=5e-07
MM6 a_61_74# a_34_4# vdd vdd PMOS_VTG L=5e-08 W=5e-07
MM0 vdd clk a_2_6# vdd PMOS_VTG L=5e-08 W=1e-06
MM5 a_34_4# a_22_6# vdd vdd PMOS_VTG L=5e-08 W=5e-07
MM4 vdd a_34_4# a_31_74# vdd PMOS_VTG L=5e-08 W=5e-07
MM3 a_31_74# a_2_6# a_22_6# vdd PMOS_VTG L=5e-08 W=5e-07
MM2 a_22_6# clk a_17_74# vdd PMOS_VTG L=5e-08 W=5e-07
MM1 a_17_74# D vdd vdd PMOS_VTG L=5e-08 W=5e-07
* c_9 a_66_6# 0 0.271997f
* c_20 clk 0 0.350944f
* c_27 Q 0 0.202617f
* c_32 a_76_84# 0 0.0210573f
* c_38 a_76_6# 0 0.0204911f
* c_45 a_34_4# 0 0.172306f
* c_55 a_2_6# 0 0.283119f
* c_59 a_22_6# 0 0.157312f
* c_64 D 0 0.0816386f
* c_73 gnd 0 0.254131f
* c_81 vdd 0 0.23624f
*
*.include "dff.pex.netlist.dff.pxi"
*
.ends
*
*
.SUBCKT sram_dff_buf_0
+ D Q Qb clk vdd gnd
* INPUT : D
* OUTPUT: Q
* OUTPUT: Qb
* INPUT : clk
* POWER : vdd
* GROUND: gnd
* inv1: 2 inv2: 4
Xdff_buf_dff
+ D qint clk vdd gnd
+ dff
Xdff_buf_inv1
+ qint Qb vdd gnd
+ sram_pinv_0
Xdff_buf_inv2
+ Qb Q vdd gnd
+ sram_pinv_1
.ENDS sram_dff_buf_0
.SUBCKT sram_dff_buf_array
+ din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd
* INPUT : din_0
* INPUT : din_1
* OUTPUT: dout_0
* OUTPUT: dout_bar_0
* OUTPUT: dout_1
* OUTPUT: dout_bar_1
* INPUT : clk
* POWER : vdd
* GROUND: gnd
* inv1: 2 inv2: 4
Xdff_r0_c0
+ din_0 dout_0 dout_bar_0 clk vdd gnd
+ sram_dff_buf_0
Xdff_r1_c0
+ din_1 dout_1 dout_bar_1 clk vdd gnd
+ sram_dff_buf_0
.ENDS sram_dff_buf_array
.SUBCKT sram_pnand2_1
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pnand2_1
.SUBCKT sram_pdriver_3
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* sizes: [1]
Xbuf_inv1
+ A Z vdd gnd
+ sram_pinv_5
.ENDS sram_pdriver_3
* spice ptx M{0} {1} nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.SUBCKT sram_pnand3_0
+ A B C Z vdd gnd
* INPUT : A
* INPUT : B
* INPUT : C
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpnand3_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand3_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand3_pmos3 Z C vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand3_nmos1 Z C net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
Mpnand3_nmos2 net1 B net2 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
Mpnand3_nmos3 net2 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pnand3_0
.SUBCKT sram_pand3_0
+ A B C Z vdd gnd
* INPUT : A
* INPUT : B
* INPUT : C
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Xpand3_nand
+ A B C zb_int vdd gnd
+ sram_pnand3_0
Xpand3_inv
+ zb_int Z vdd gnd
+ sram_pdriver_3
.ENDS sram_pand3_0
.SUBCKT sram_pinv_10
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01p ad=0.01p
.ENDS sram_pinv_10
.SUBCKT sram_delay_chain
+ in out vdd gnd
* INPUT : in
* OUTPUT: out
* POWER : vdd
* GROUND: gnd
* fanouts: [4, 4, 4, 4, 4, 4, 4, 4, 4]
Xdinv0
+ in dout_1 vdd gnd
+ sram_pinv_10
Xdload_0_0
+ dout_1 n_0_0 vdd gnd
+ sram_pinv_10
Xdload_0_1
+ dout_1 n_0_1 vdd gnd
+ sram_pinv_10
Xdload_0_2
+ dout_1 n_0_2 vdd gnd
+ sram_pinv_10
Xdload_0_3
+ dout_1 n_0_3 vdd gnd
+ sram_pinv_10
Xdinv1
+ dout_1 dout_2 vdd gnd
+ sram_pinv_10
Xdload_1_0
+ dout_2 n_1_0 vdd gnd
+ sram_pinv_10
Xdload_1_1
+ dout_2 n_1_1 vdd gnd
+ sram_pinv_10
Xdload_1_2
+ dout_2 n_1_2 vdd gnd
+ sram_pinv_10
Xdload_1_3
+ dout_2 n_1_3 vdd gnd
+ sram_pinv_10
Xdinv2
+ dout_2 dout_3 vdd gnd
+ sram_pinv_10
Xdload_2_0
+ dout_3 n_2_0 vdd gnd
+ sram_pinv_10
Xdload_2_1
+ dout_3 n_2_1 vdd gnd
+ sram_pinv_10
Xdload_2_2
+ dout_3 n_2_2 vdd gnd
+ sram_pinv_10
Xdload_2_3
+ dout_3 n_2_3 vdd gnd
+ sram_pinv_10
Xdinv3
+ dout_3 dout_4 vdd gnd
+ sram_pinv_10
Xdload_3_0
+ dout_4 n_3_0 vdd gnd
+ sram_pinv_10
Xdload_3_1
+ dout_4 n_3_1 vdd gnd
+ sram_pinv_10
Xdload_3_2
+ dout_4 n_3_2 vdd gnd
+ sram_pinv_10
Xdload_3_3
+ dout_4 n_3_3 vdd gnd
+ sram_pinv_10
Xdinv4
+ dout_4 dout_5 vdd gnd
+ sram_pinv_10
Xdload_4_0
+ dout_5 n_4_0 vdd gnd
+ sram_pinv_10
Xdload_4_1
+ dout_5 n_4_1 vdd gnd
+ sram_pinv_10
Xdload_4_2
+ dout_5 n_4_2 vdd gnd
+ sram_pinv_10
Xdload_4_3
+ dout_5 n_4_3 vdd gnd
+ sram_pinv_10
Xdinv5
+ dout_5 dout_6 vdd gnd
+ sram_pinv_10
Xdload_5_0
+ dout_6 n_5_0 vdd gnd
+ sram_pinv_10
Xdload_5_1
+ dout_6 n_5_1 vdd gnd
+ sram_pinv_10
Xdload_5_2
+ dout_6 n_5_2 vdd gnd
+ sram_pinv_10
Xdload_5_3
+ dout_6 n_5_3 vdd gnd
+ sram_pinv_10
Xdinv6
+ dout_6 dout_7 vdd gnd
+ sram_pinv_10
Xdload_6_0
+ dout_7 n_6_0 vdd gnd
+ sram_pinv_10
Xdload_6_1
+ dout_7 n_6_1 vdd gnd
+ sram_pinv_10
Xdload_6_2
+ dout_7 n_6_2 vdd gnd
+ sram_pinv_10
Xdload_6_3
+ dout_7 n_6_3 vdd gnd
+ sram_pinv_10
Xdinv7
+ dout_7 dout_8 vdd gnd
+ sram_pinv_10
Xdload_7_0
+ dout_8 n_7_0 vdd gnd
+ sram_pinv_10
Xdload_7_1
+ dout_8 n_7_1 vdd gnd
+ sram_pinv_10
Xdload_7_2
+ dout_8 n_7_2 vdd gnd
+ sram_pinv_10
Xdload_7_3
+ dout_8 n_7_3 vdd gnd
+ sram_pinv_10
Xdinv8
+ dout_8 out vdd gnd
+ sram_pinv_10
Xdload_8_0
+ out n_8_0 vdd gnd
+ sram_pinv_10
Xdload_8_1
+ out n_8_1 vdd gnd
+ sram_pinv_10
Xdload_8_2
+ out n_8_2 vdd gnd
+ sram_pinv_10
Xdload_8_3
+ out n_8_3 vdd gnd
+ sram_pinv_10
.ENDS sram_delay_chain
* spice ptx M{0} {1} nmos_vtg m=4 w=0.2925u l=0.05u pd=0.68u ps=0.68u as=0.04p ad=0.04p
* spice ptx M{0} {1} pmos_vtg m=4 w=0.8775000000000001u l=0.05u pd=1.86u ps=1.86u as=0.11p ad=0.11p
.SUBCKT sram_pinv_7
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=4 w=0.8775000000000001u l=0.05u pd=1.86u ps=1.86u as=0.11p ad=0.11p
Mpinv_nmos Z A gnd gnd nmos_vtg m=4 w=0.2925u l=0.05u pd=0.68u ps=0.68u as=0.04p ad=0.04p
.ENDS sram_pinv_7
.SUBCKT sram_pinv_6
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=2 w=0.54u l=0.05u pd=1.18u ps=1.18u as=0.07p ad=0.07p
Mpinv_nmos Z A gnd gnd nmos_vtg m=2 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pinv_6
.SUBCKT sram_pdriver_0
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* sizes: [1, 1, 4, 13]
Xbuf_inv1
+ A Zb1_int vdd gnd
+ sram_pinv_5
Xbuf_inv2
+ Zb1_int Zb2_int vdd gnd
+ sram_pinv_5
Xbuf_inv3
+ Zb2_int Zb3_int vdd gnd
+ sram_pinv_6
Xbuf_inv4
+ Zb3_int Z vdd gnd
+ sram_pinv_7
.ENDS sram_pdriver_0
* spice ptx M{0} {1} pmos_vtg m=3 w=0.81u l=0.05u pd=1.72u ps=1.72u as=0.10p ad=0.10p
* spice ptx M{0} {1} nmos_vtg m=3 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
.SUBCKT sram_pinv_9
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=3 w=0.81u l=0.05u pd=1.72u ps=1.72u as=0.10p ad=0.10p
Mpinv_nmos Z A gnd gnd nmos_vtg m=3 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
.ENDS sram_pinv_9
.SUBCKT sram_pdriver_2
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* sizes: [9]
Xbuf_inv1
+ A Z vdd gnd
+ sram_pinv_9
.ENDS sram_pdriver_2
.SUBCKT sram_pand3
+ A B C Z vdd gnd
* INPUT : A
* INPUT : B
* INPUT : C
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Xpand3_nand
+ A B C zb_int vdd gnd
+ sram_pnand3_0
Xpand3_inv
+ zb_int Z vdd gnd
+ sram_pdriver_2
.ENDS sram_pand3
.SUBCKT sram_pdriver_4
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* sizes: [1, 1]
Xbuf_inv1
+ A Zb1_int vdd gnd
+ sram_pinv_5
Xbuf_inv2
+ Zb1_int Z vdd gnd
+ sram_pinv_5
.ENDS sram_pdriver_4
.SUBCKT sram_control_logic_rw
+ csb web clk rbl_bl s_en w_en p_en_bar wl_en clk_buf vdd gnd
* INPUT : csb
* INPUT : web
* INPUT : clk
* INPUT : rbl_bl
* OUTPUT: s_en
* OUTPUT: w_en
* OUTPUT: p_en_bar
* OUTPUT: wl_en
* OUTPUT: clk_buf
* POWER : vdd
* GROUND: gnd
* word_size 1
Xctrl_dffs
+ csb web cs_bar cs we_bar we clk_buf vdd gnd
+ sram_dff_buf_array
Xclkbuf
+ clk clk_buf vdd gnd
+ sram_pdriver_0
Xinv_clk_bar
+ clk_buf clk_bar vdd gnd
+ sram_pinv_3
Xand2_gated_clk_bar
+ clk_bar cs gated_clk_bar vdd gnd
+ sram_pand2
Xand2_gated_clk_buf
+ clk_buf cs gated_clk_buf vdd gnd
+ sram_pand2
Xbuf_wl_en
+ gated_clk_bar wl_en vdd gnd
+ sram_pdriver_1
Xrbl_bl_delay_inv
+ rbl_bl_delay rbl_bl_delay_bar vdd gnd
+ sram_pinv_3
Xw_en_and
+ we rbl_bl_delay_bar gated_clk_bar w_en vdd gnd
+ sram_pand3
Xbuf_s_en_and
+ rbl_bl_delay gated_clk_bar we_bar s_en vdd gnd
+ sram_pand3_0
Xdelay_chain
+ rbl_bl rbl_bl_delay vdd gnd
+ sram_delay_chain
Xnand_p_en_bar
+ gated_clk_buf rbl_bl_delay p_en_bar_unbuf vdd gnd
+ sram_pnand2_1
Xbuf_p_en_bar
+ p_en_bar_unbuf p_en_bar vdd gnd
+ sram_pdriver_4
.ENDS sram_control_logic_rw
.SUBCKT sense_amp bl br dout en vdd gnd
M_1 dint net_1 vdd vdd pmos_vtg w=540.0n l=50.0n
M_3 net_1 dint vdd vdd pmos_vtg w=540.0n l=50.0n
M_2 dint net_1 net_2 gnd nmos_vtg w=270.0n l=50.0n
M_8 net_1 dint net_2 gnd nmos_vtg w=270.0n l=50.0n
M_5 bl en dint vdd pmos_vtg w=720.0n l=50.0n
M_6 br en net_1 vdd pmos_vtg w=720.0n l=50.0n
M_7 net_2 en gnd gnd nmos_vtg w=270.0n l=50.0n
M_8 dout_bar dint vdd vdd pmos_vtg w=180.0n l=50.0n
M_9 dout_bar dint gnd gnd nmos_vtg w=90.0n l=50.0n
M_10 dout dout_bar vdd vdd pmos_vtg w=540.0n l=50.0n
M_11 dout dout_bar gnd gnd nmos_vtg w=270.0n l=50.0n
.ENDS sense_amp
.SUBCKT sram_sense_amp_array
+ data_0 bl_0 br_0 en vdd gnd
* OUTPUT: data_0
* INPUT : bl_0
* INPUT : br_0
* INPUT : en
* POWER : vdd
* GROUND: gnd
* words_per_row: 1
Xsa_d0
+ bl_0 br_0 data_0 en vdd gnd
+ sense_amp
.ENDS sram_sense_amp_array
.SUBCKT sram_precharge_0
+ bl br en_bar vdd
* OUTPUT: bl
* OUTPUT: br
* INPUT : en_bar
* POWER : vdd
Mlower_pmos bl en_bar br vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mupper_pmos1 bl en_bar vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mupper_pmos2 br en_bar vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
.ENDS sram_precharge_0
.SUBCKT sram_precharge_array
+ bl_0 br_0 bl_1 br_1 en_bar vdd
* OUTPUT: bl_0
* OUTPUT: br_0
* OUTPUT: bl_1
* OUTPUT: br_1
* INPUT : en_bar
* POWER : vdd
* cols: 2 size: 1 bl: bl br: br
Xpre_column_0
+ bl_0 br_0 en_bar vdd
+ sram_precharge_0
Xpre_column_1
+ bl_1 br_1 en_bar vdd
+ sram_precharge_0
.ENDS sram_precharge_array
.SUBCKT write_driver din bl br en vdd gnd
*inverters for enable and data input
minP bl_bar din vdd vdd pmos_vtg w=360.000000n l=50.000000n
minN bl_bar din gnd gnd nmos_vtg w=180.000000n l=50.000000n
moutP en_bar en vdd vdd pmos_vtg w=360.000000n l=50.000000n
moutN en_bar en gnd gnd nmos_vtg w=180.000000n l=50.000000n
*tristate for BL
mout0P int1 bl_bar vdd vdd pmos_vtg w=360.000000n l=50.000000n
mout0P2 bl en_bar int1 vdd pmos_vtg w=360.000000n l=50.000000n
mout0N bl en int2 gnd nmos_vtg w=180.000000n l=50.000000n
mout0N2 int2 bl_bar gnd gnd nmos_vtg w=180.000000n l=50.000000n
*tristate for BR
mout1P int3 din vdd vdd pmos_vtg w=360.000000n l=50.000000n
mout1P2 br en_bar int3 vdd pmos_vtg w=360.000000n l=50.000000n
mout1N br en int4 gnd nmos_vtg w=180.000000n l=50.000000n
mout1N2 int4 din gnd gnd nmos_vtg w=180.000000n l=50.000000n
.ENDS write_driver
.SUBCKT sram_write_driver_array
+ data_0 bl_0 br_0 en vdd gnd
* INPUT : data_0
* OUTPUT: bl_0
* OUTPUT: br_0
* INPUT : en
* POWER : vdd
* GROUND: gnd
* word_size 1
Xwrite_driver0
+ data_0 bl_0 br_0 en vdd gnd
+ write_driver
.ENDS sram_write_driver_array
.SUBCKT sram_port_data
+ rbl_bl rbl_br bl_0 br_0 dout_0 din_0 s_en p_en_bar w_en vdd gnd
* INOUT : rbl_bl
* INOUT : rbl_br
* INOUT : bl_0
* INOUT : br_0
* OUTPUT: dout_0
* INPUT : din_0
* INPUT : s_en
* INPUT : p_en_bar
* INPUT : w_en
* POWER : vdd
* GROUND: gnd
Xprecharge_array0
+ rbl_bl rbl_br bl_0 br_0 p_en_bar vdd
+ sram_precharge_array
Xsense_amp_array0
+ dout_0 bl_0 br_0 s_en vdd gnd
+ sram_sense_amp_array
Xwrite_driver_array0
+ din_0 bl_0 br_0 w_en vdd gnd
+ sram_write_driver_array
.ENDS sram_port_data
.SUBCKT sram_pnand2
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.02p ad=0.02p
.ENDS sram_pnand2
.SUBCKT sram_pinv
+ A Z vdd gnd
* INPUT : A
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03p ad=0.03p
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01p ad=0.01p
.ENDS sram_pinv
.SUBCKT sram_and2_dec_0
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* size: 1
Xpand2_dec_nand
+ A B zb_int vdd gnd
+ sram_pnand2
Xpand2_dec_inv
+ zb_int Z vdd gnd
+ sram_pinv
.ENDS sram_and2_dec_0
.SUBCKT sram_and2_dec
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
* size: 1
Xpand2_dec_nand
+ A B zb_int vdd gnd
+ sram_pnand2
Xpand2_dec_inv
+ zb_int Z vdd gnd
+ sram_pinv
.ENDS sram_and2_dec
.SUBCKT sram_hierarchical_predecode2x4
+ in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd
* INPUT : in_0
* INPUT : in_1
* OUTPUT: out_0
* OUTPUT: out_1
* OUTPUT: out_2
* OUTPUT: out_3
* POWER : vdd
* GROUND: gnd
Xpre_inv_0
+ in_0 inbar_0 vdd gnd
+ sram_pinv
Xpre_inv_1
+ in_1 inbar_1 vdd gnd
+ sram_pinv
XXpre2x4_and_0
+ inbar_0 inbar_1 out_0 vdd gnd
+ sram_and2_dec
XXpre2x4_and_1
+ in_0 inbar_1 out_1 vdd gnd
+ sram_and2_dec
XXpre2x4_and_2
+ inbar_0 in_1 out_2 vdd gnd
+ sram_and2_dec
XXpre2x4_and_3
+ in_0 in_1 out_3 vdd gnd
+ sram_and2_dec
.ENDS sram_hierarchical_predecode2x4
.SUBCKT sram_hierarchical_decoder
+ addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3
+ decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10
+ decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd
* INPUT : addr_0
* INPUT : addr_1
* INPUT : addr_2
* INPUT : addr_3
* OUTPUT: decode_0
* OUTPUT: decode_1
* OUTPUT: decode_2
* OUTPUT: decode_3
* OUTPUT: decode_4
* OUTPUT: decode_5
* OUTPUT: decode_6
* OUTPUT: decode_7
* OUTPUT: decode_8
* OUTPUT: decode_9
* OUTPUT: decode_10
* OUTPUT: decode_11
* OUTPUT: decode_12
* OUTPUT: decode_13
* OUTPUT: decode_14
* OUTPUT: decode_15
* POWER : vdd
* GROUND: gnd
Xpre_0
+ addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd
+ sram_hierarchical_predecode2x4
Xpre_1
+ addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd
+ sram_hierarchical_predecode2x4
XDEC_AND_0
+ out_0 out_4 decode_0 vdd gnd
+ sram_and2_dec
XDEC_AND_4
+ out_0 out_5 decode_4 vdd gnd
+ sram_and2_dec
XDEC_AND_8
+ out_0 out_6 decode_8 vdd gnd
+ sram_and2_dec
XDEC_AND_12
+ out_0 out_7 decode_12 vdd gnd
+ sram_and2_dec
XDEC_AND_1
+ out_1 out_4 decode_1 vdd gnd
+ sram_and2_dec
XDEC_AND_5
+ out_1 out_5 decode_5 vdd gnd
+ sram_and2_dec
XDEC_AND_9
+ out_1 out_6 decode_9 vdd gnd
+ sram_and2_dec
XDEC_AND_13
+ out_1 out_7 decode_13 vdd gnd
+ sram_and2_dec
XDEC_AND_2
+ out_2 out_4 decode_2 vdd gnd
+ sram_and2_dec
XDEC_AND_6
+ out_2 out_5 decode_6 vdd gnd
+ sram_and2_dec
XDEC_AND_10
+ out_2 out_6 decode_10 vdd gnd
+ sram_and2_dec
XDEC_AND_14
+ out_2 out_7 decode_14 vdd gnd
+ sram_and2_dec
XDEC_AND_3
+ out_3 out_4 decode_3 vdd gnd
+ sram_and2_dec
XDEC_AND_7
+ out_3 out_5 decode_7 vdd gnd
+ sram_and2_dec
XDEC_AND_11
+ out_3 out_6 decode_11 vdd gnd
+ sram_and2_dec
XDEC_AND_15
+ out_3 out_7 decode_15 vdd gnd
+ sram_and2_dec
.ENDS sram_hierarchical_decoder
.SUBCKT sram_wordline_driver
+ A B Z vdd gnd
* INPUT : A
* INPUT : B
* OUTPUT: Z
* POWER : vdd
* GROUND: gnd
Xwld_nand
+ A B zb_int vdd gnd
+ sram_pnand2
Xwl_driver
+ zb_int Z vdd gnd
+ sram_pinv
.ENDS sram_wordline_driver
.SUBCKT sram_wordline_driver_array
+ in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12
+ in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9
+ wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en vdd gnd
* INPUT : in_0
* INPUT : in_1
* INPUT : in_2
* INPUT : in_3
* INPUT : in_4
* INPUT : in_5
* INPUT : in_6
* INPUT : in_7
* INPUT : in_8
* INPUT : in_9
* INPUT : in_10
* INPUT : in_11
* INPUT : in_12
* INPUT : in_13
* INPUT : in_14
* INPUT : in_15
* OUTPUT: wl_0
* OUTPUT: wl_1
* OUTPUT: wl_2
* OUTPUT: wl_3
* OUTPUT: wl_4
* OUTPUT: wl_5
* OUTPUT: wl_6
* OUTPUT: wl_7
* OUTPUT: wl_8
* OUTPUT: wl_9
* OUTPUT: wl_10
* OUTPUT: wl_11
* OUTPUT: wl_12
* OUTPUT: wl_13
* OUTPUT: wl_14
* OUTPUT: wl_15
* INPUT : en
* POWER : vdd
* GROUND: gnd
* rows: 16 cols: 1
Xwl_driver_and0
+ in_0 en wl_0 vdd gnd
+ sram_wordline_driver
Xwl_driver_and1
+ in_1 en wl_1 vdd gnd
+ sram_wordline_driver
Xwl_driver_and2
+ in_2 en wl_2 vdd gnd
+ sram_wordline_driver
Xwl_driver_and3
+ in_3 en wl_3 vdd gnd
+ sram_wordline_driver
Xwl_driver_and4
+ in_4 en wl_4 vdd gnd
+ sram_wordline_driver
Xwl_driver_and5
+ in_5 en wl_5 vdd gnd
+ sram_wordline_driver
Xwl_driver_and6
+ in_6 en wl_6 vdd gnd
+ sram_wordline_driver
Xwl_driver_and7
+ in_7 en wl_7 vdd gnd
+ sram_wordline_driver
Xwl_driver_and8
+ in_8 en wl_8 vdd gnd
+ sram_wordline_driver
Xwl_driver_and9
+ in_9 en wl_9 vdd gnd
+ sram_wordline_driver
Xwl_driver_and10
+ in_10 en wl_10 vdd gnd
+ sram_wordline_driver
Xwl_driver_and11
+ in_11 en wl_11 vdd gnd
+ sram_wordline_driver
Xwl_driver_and12
+ in_12 en wl_12 vdd gnd
+ sram_wordline_driver
Xwl_driver_and13
+ in_13 en wl_13 vdd gnd
+ sram_wordline_driver
Xwl_driver_and14
+ in_14 en wl_14 vdd gnd
+ sram_wordline_driver
Xwl_driver_and15
+ in_15 en wl_15 vdd gnd
+ sram_wordline_driver
.ENDS sram_wordline_driver_array
.SUBCKT sram_port_address
+ addr_0 addr_1 addr_2 addr_3 wl_en wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6
+ wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 rbl_wl vdd gnd
* INPUT : addr_0
* INPUT : addr_1
* INPUT : addr_2
* INPUT : addr_3
* INPUT : wl_en
* OUTPUT: wl_0
* OUTPUT: wl_1
* OUTPUT: wl_2
* OUTPUT: wl_3
* OUTPUT: wl_4
* OUTPUT: wl_5
* OUTPUT: wl_6
* OUTPUT: wl_7
* OUTPUT: wl_8
* OUTPUT: wl_9
* OUTPUT: wl_10
* OUTPUT: wl_11
* OUTPUT: wl_12
* OUTPUT: wl_13
* OUTPUT: wl_14
* OUTPUT: wl_15
* OUTPUT: rbl_wl
* POWER : vdd
* GROUND: gnd
Xrow_decoder
+ addr_0 addr_1 addr_2 addr_3 dec_out_0 dec_out_1 dec_out_2 dec_out_3
+ dec_out_4 dec_out_5 dec_out_6 dec_out_7 dec_out_8 dec_out_9 dec_out_10
+ dec_out_11 dec_out_12 dec_out_13 dec_out_14 dec_out_15 vdd gnd
+ sram_hierarchical_decoder
Xwordline_driver
+ dec_out_0 dec_out_1 dec_out_2 dec_out_3 dec_out_4 dec_out_5 dec_out_6
+ dec_out_7 dec_out_8 dec_out_9 dec_out_10 dec_out_11 dec_out_12
+ dec_out_13 dec_out_14 dec_out_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6
+ wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 wl_en vdd gnd
+ sram_wordline_driver_array
Xrbl_driver
+ wl_en vdd rbl_wl vdd gnd
+ sram_and2_dec_0
.ENDS sram_port_address
.SUBCKT dummy_cell_1rw bl br wl vdd gnd
* Inverter 1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
* Inverer 2
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n
.ENDS dummy_cell_1rw
.SUBCKT sram_dummy_array_2
+ bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7
+ wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16
+ wl_0_17 wl_0_18 vdd gnd
* INOUT : bl_0_0
* INOUT : br_0_0
* INPUT : wl_0_0
* INPUT : wl_0_1
* INPUT : wl_0_2
* INPUT : wl_0_3
* INPUT : wl_0_4
* INPUT : wl_0_5
* INPUT : wl_0_6
* INPUT : wl_0_7
* INPUT : wl_0_8
* INPUT : wl_0_9
* INPUT : wl_0_10
* INPUT : wl_0_11
* INPUT : wl_0_12
* INPUT : wl_0_13
* INPUT : wl_0_14
* INPUT : wl_0_15
* INPUT : wl_0_16
* INPUT : wl_0_17
* INPUT : wl_0_18
* POWER : vdd
* GROUND: gnd
Xbit_r0_c0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ dummy_cell_1rw
Xbit_r1_c0
+ bl_0_0 br_0_0 wl_0_1 vdd gnd
+ dummy_cell_1rw
Xbit_r2_c0
+ bl_0_0 br_0_0 wl_0_2 vdd gnd
+ dummy_cell_1rw
Xbit_r3_c0
+ bl_0_0 br_0_0 wl_0_3 vdd gnd
+ dummy_cell_1rw
Xbit_r4_c0
+ bl_0_0 br_0_0 wl_0_4 vdd gnd
+ dummy_cell_1rw
Xbit_r5_c0
+ bl_0_0 br_0_0 wl_0_5 vdd gnd
+ dummy_cell_1rw
Xbit_r6_c0
+ bl_0_0 br_0_0 wl_0_6 vdd gnd
+ dummy_cell_1rw
Xbit_r7_c0
+ bl_0_0 br_0_0 wl_0_7 vdd gnd
+ dummy_cell_1rw
Xbit_r8_c0
+ bl_0_0 br_0_0 wl_0_8 vdd gnd
+ dummy_cell_1rw
Xbit_r9_c0
+ bl_0_0 br_0_0 wl_0_9 vdd gnd
+ dummy_cell_1rw
Xbit_r10_c0
+ bl_0_0 br_0_0 wl_0_10 vdd gnd
+ dummy_cell_1rw
Xbit_r11_c0
+ bl_0_0 br_0_0 wl_0_11 vdd gnd
+ dummy_cell_1rw
Xbit_r12_c0
+ bl_0_0 br_0_0 wl_0_12 vdd gnd
+ dummy_cell_1rw
Xbit_r13_c0
+ bl_0_0 br_0_0 wl_0_13 vdd gnd
+ dummy_cell_1rw
Xbit_r14_c0
+ bl_0_0 br_0_0 wl_0_14 vdd gnd
+ dummy_cell_1rw
Xbit_r15_c0
+ bl_0_0 br_0_0 wl_0_15 vdd gnd
+ dummy_cell_1rw
Xbit_r16_c0
+ bl_0_0 br_0_0 wl_0_16 vdd gnd
+ dummy_cell_1rw
Xbit_r17_c0
+ bl_0_0 br_0_0 wl_0_17 vdd gnd
+ dummy_cell_1rw
Xbit_r18_c0
+ bl_0_0 br_0_0 wl_0_18 vdd gnd
+ dummy_cell_1rw
.ENDS sram_dummy_array_2
.SUBCKT sram_dummy_array_3
+ bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7
+ wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16
+ wl_0_17 wl_0_18 vdd gnd
* INOUT : bl_0_0
* INOUT : br_0_0
* INPUT : wl_0_0
* INPUT : wl_0_1
* INPUT : wl_0_2
* INPUT : wl_0_3
* INPUT : wl_0_4
* INPUT : wl_0_5
* INPUT : wl_0_6
* INPUT : wl_0_7
* INPUT : wl_0_8
* INPUT : wl_0_9
* INPUT : wl_0_10
* INPUT : wl_0_11
* INPUT : wl_0_12
* INPUT : wl_0_13
* INPUT : wl_0_14
* INPUT : wl_0_15
* INPUT : wl_0_16
* INPUT : wl_0_17
* INPUT : wl_0_18
* POWER : vdd
* GROUND: gnd
Xbit_r0_c0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ dummy_cell_1rw
Xbit_r1_c0
+ bl_0_0 br_0_0 wl_0_1 vdd gnd
+ dummy_cell_1rw
Xbit_r2_c0
+ bl_0_0 br_0_0 wl_0_2 vdd gnd
+ dummy_cell_1rw
Xbit_r3_c0
+ bl_0_0 br_0_0 wl_0_3 vdd gnd
+ dummy_cell_1rw
Xbit_r4_c0
+ bl_0_0 br_0_0 wl_0_4 vdd gnd
+ dummy_cell_1rw
Xbit_r5_c0
+ bl_0_0 br_0_0 wl_0_5 vdd gnd
+ dummy_cell_1rw
Xbit_r6_c0
+ bl_0_0 br_0_0 wl_0_6 vdd gnd
+ dummy_cell_1rw
Xbit_r7_c0
+ bl_0_0 br_0_0 wl_0_7 vdd gnd
+ dummy_cell_1rw
Xbit_r8_c0
+ bl_0_0 br_0_0 wl_0_8 vdd gnd
+ dummy_cell_1rw
Xbit_r9_c0
+ bl_0_0 br_0_0 wl_0_9 vdd gnd
+ dummy_cell_1rw
Xbit_r10_c0
+ bl_0_0 br_0_0 wl_0_10 vdd gnd
+ dummy_cell_1rw
Xbit_r11_c0
+ bl_0_0 br_0_0 wl_0_11 vdd gnd
+ dummy_cell_1rw
Xbit_r12_c0
+ bl_0_0 br_0_0 wl_0_12 vdd gnd
+ dummy_cell_1rw
Xbit_r13_c0
+ bl_0_0 br_0_0 wl_0_13 vdd gnd
+ dummy_cell_1rw
Xbit_r14_c0
+ bl_0_0 br_0_0 wl_0_14 vdd gnd
+ dummy_cell_1rw
Xbit_r15_c0
+ bl_0_0 br_0_0 wl_0_15 vdd gnd
+ dummy_cell_1rw
Xbit_r16_c0
+ bl_0_0 br_0_0 wl_0_16 vdd gnd
+ dummy_cell_1rw
Xbit_r17_c0
+ bl_0_0 br_0_0 wl_0_17 vdd gnd
+ dummy_cell_1rw
Xbit_r18_c0
+ bl_0_0 br_0_0 wl_0_18 vdd gnd
+ dummy_cell_1rw
.ENDS sram_dummy_array_3
.SUBCKT sram_dummy_array
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
* INOUT : bl_0_0
* INOUT : br_0_0
* INPUT : wl_0_0
* POWER : vdd
* GROUND: gnd
Xbit_r0_c0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ dummy_cell_1rw
.ENDS sram_dummy_array
.SUBCKT cell_1rw bl br wl vdd gnd
* Inverter 1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
* Inverer 2
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br wl Q_bar gnd NMOS_VTG W=135.00n L=50n
.ENDS cell_1rw
.SUBCKT sram_bitcell_array
+ bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7
+ wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd
* INOUT : bl_0_0
* INOUT : br_0_0
* INPUT : wl_0_0
* INPUT : wl_0_1
* INPUT : wl_0_2
* INPUT : wl_0_3
* INPUT : wl_0_4
* INPUT : wl_0_5
* INPUT : wl_0_6
* INPUT : wl_0_7
* INPUT : wl_0_8
* INPUT : wl_0_9
* INPUT : wl_0_10
* INPUT : wl_0_11
* INPUT : wl_0_12
* INPUT : wl_0_13
* INPUT : wl_0_14
* INPUT : wl_0_15
* POWER : vdd
* GROUND: gnd
* rows: 16 cols: 1
Xbit_r0_c0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ cell_1rw
Xbit_r1_c0
+ bl_0_0 br_0_0 wl_0_1 vdd gnd
+ cell_1rw
Xbit_r2_c0
+ bl_0_0 br_0_0 wl_0_2 vdd gnd
+ cell_1rw
Xbit_r3_c0
+ bl_0_0 br_0_0 wl_0_3 vdd gnd
+ cell_1rw
Xbit_r4_c0
+ bl_0_0 br_0_0 wl_0_4 vdd gnd
+ cell_1rw
Xbit_r5_c0
+ bl_0_0 br_0_0 wl_0_5 vdd gnd
+ cell_1rw
Xbit_r6_c0
+ bl_0_0 br_0_0 wl_0_6 vdd gnd
+ cell_1rw
Xbit_r7_c0
+ bl_0_0 br_0_0 wl_0_7 vdd gnd
+ cell_1rw
Xbit_r8_c0
+ bl_0_0 br_0_0 wl_0_8 vdd gnd
+ cell_1rw
Xbit_r9_c0
+ bl_0_0 br_0_0 wl_0_9 vdd gnd
+ cell_1rw
Xbit_r10_c0
+ bl_0_0 br_0_0 wl_0_10 vdd gnd
+ cell_1rw
Xbit_r11_c0
+ bl_0_0 br_0_0 wl_0_11 vdd gnd
+ cell_1rw
Xbit_r12_c0
+ bl_0_0 br_0_0 wl_0_12 vdd gnd
+ cell_1rw
Xbit_r13_c0
+ bl_0_0 br_0_0 wl_0_13 vdd gnd
+ cell_1rw
Xbit_r14_c0
+ bl_0_0 br_0_0 wl_0_14 vdd gnd
+ cell_1rw
Xbit_r15_c0
+ bl_0_0 br_0_0 wl_0_15 vdd gnd
+ cell_1rw
.ENDS sram_bitcell_array
.SUBCKT replica_cell_1rw bl br wl vdd gnd
* Inverter 1
MM0 vdd Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 vdd Q vdd vdd PMOS_VTG W=90n L=50n
* Inverer 2
MM1 Q vdd gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q vdd vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br wl vdd gnd NMOS_VTG W=135.00n L=50n
.ENDS cell_1rw
.SUBCKT sram_replica_column
+ bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7
+ wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 wl_0_16
+ vdd gnd
* OUTPUT: bl_0_0
* OUTPUT: br_0_0
* INPUT : wl_0_0
* INPUT : wl_0_1
* INPUT : wl_0_2
* INPUT : wl_0_3
* INPUT : wl_0_4
* INPUT : wl_0_5
* INPUT : wl_0_6
* INPUT : wl_0_7
* INPUT : wl_0_8
* INPUT : wl_0_9
* INPUT : wl_0_10
* INPUT : wl_0_11
* INPUT : wl_0_12
* INPUT : wl_0_13
* INPUT : wl_0_14
* INPUT : wl_0_15
* INPUT : wl_0_16
* POWER : vdd
* GROUND: gnd
Xrbc_0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ replica_cell_1rw
Xrbc_1
+ bl_0_0 br_0_0 wl_0_1 vdd gnd
+ replica_cell_1rw
Xrbc_2
+ bl_0_0 br_0_0 wl_0_2 vdd gnd
+ replica_cell_1rw
Xrbc_3
+ bl_0_0 br_0_0 wl_0_3 vdd gnd
+ replica_cell_1rw
Xrbc_4
+ bl_0_0 br_0_0 wl_0_4 vdd gnd
+ replica_cell_1rw
Xrbc_5
+ bl_0_0 br_0_0 wl_0_5 vdd gnd
+ replica_cell_1rw
Xrbc_6
+ bl_0_0 br_0_0 wl_0_6 vdd gnd
+ replica_cell_1rw
Xrbc_7
+ bl_0_0 br_0_0 wl_0_7 vdd gnd
+ replica_cell_1rw
Xrbc_8
+ bl_0_0 br_0_0 wl_0_8 vdd gnd
+ replica_cell_1rw
Xrbc_9
+ bl_0_0 br_0_0 wl_0_9 vdd gnd
+ replica_cell_1rw
Xrbc_10
+ bl_0_0 br_0_0 wl_0_10 vdd gnd
+ replica_cell_1rw
Xrbc_11
+ bl_0_0 br_0_0 wl_0_11 vdd gnd
+ replica_cell_1rw
Xrbc_12
+ bl_0_0 br_0_0 wl_0_12 vdd gnd
+ replica_cell_1rw
Xrbc_13
+ bl_0_0 br_0_0 wl_0_13 vdd gnd
+ replica_cell_1rw
Xrbc_14
+ bl_0_0 br_0_0 wl_0_14 vdd gnd
+ replica_cell_1rw
Xrbc_15
+ bl_0_0 br_0_0 wl_0_15 vdd gnd
+ replica_cell_1rw
Xrbc_16
+ bl_0_0 br_0_0 wl_0_16 vdd gnd
+ replica_cell_1rw
.ENDS sram_replica_column
.SUBCKT sram_replica_bitcell_array
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2
+ wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11
+ wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd
* INOUT : rbl_bl_0_0
* INOUT : rbl_br_0_0
* INOUT : bl_0_0
* INOUT : br_0_0
* INPUT : rbl_wl_0_0
* INPUT : wl_0_0
* INPUT : wl_0_1
* INPUT : wl_0_2
* INPUT : wl_0_3
* INPUT : wl_0_4
* INPUT : wl_0_5
* INPUT : wl_0_6
* INPUT : wl_0_7
* INPUT : wl_0_8
* INPUT : wl_0_9
* INPUT : wl_0_10
* INPUT : wl_0_11
* INPUT : wl_0_12
* INPUT : wl_0_13
* INPUT : wl_0_14
* INPUT : wl_0_15
* POWER : vdd
* GROUND: gnd
* rbl: [1, 0] left_rbl: [0] right_rbl: []
Xbitcell_array
+ bl_0_0 br_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7
+ wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd
+ sram_bitcell_array
Xreplica_col_0
+ rbl_bl_0_0 rbl_br_0_0 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2 wl_0_3 wl_0_4
+ wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12 wl_0_13
+ wl_0_14 wl_0_15 vdd gnd
+ sram_replica_column
Xdummy_row_0
+ bl_0_0 br_0_0 rbl_wl_0_0 vdd gnd
+ sram_dummy_array
.ENDS sram_replica_bitcell_array
.SUBCKT sram_dummy_array_0
+ bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd
* INOUT : bl_0_0
* INOUT : br_0_0
* INOUT : bl_0_1
* INOUT : br_0_1
* INPUT : wl_0_0
* POWER : vdd
* GROUND: gnd
Xbit_r0_c0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ dummy_cell_1rw
Xbit_r0_c1
+ bl_0_1 br_0_1 wl_0_0 vdd gnd
+ dummy_cell_1rw
.ENDS sram_dummy_array_0
.SUBCKT sram_dummy_array_1
+ bl_0_0 br_0_0 bl_0_1 br_0_1 wl_0_0 vdd gnd
* INOUT : bl_0_0
* INOUT : br_0_0
* INOUT : bl_0_1
* INOUT : br_0_1
* INPUT : wl_0_0
* POWER : vdd
* GROUND: gnd
Xbit_r0_c0
+ bl_0_0 br_0_0 wl_0_0 vdd gnd
+ dummy_cell_1rw
Xbit_r0_c1
+ bl_0_1 br_0_1 wl_0_0 vdd gnd
+ dummy_cell_1rw
.ENDS sram_dummy_array_1
.SUBCKT sram_capped_replica_bitcell_array
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2
+ wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11
+ wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd
* INOUT : rbl_bl_0_0
* INOUT : rbl_br_0_0
* INOUT : bl_0_0
* INOUT : br_0_0
* INPUT : rbl_wl_0_0
* INPUT : wl_0_0
* INPUT : wl_0_1
* INPUT : wl_0_2
* INPUT : wl_0_3
* INPUT : wl_0_4
* INPUT : wl_0_5
* INPUT : wl_0_6
* INPUT : wl_0_7
* INPUT : wl_0_8
* INPUT : wl_0_9
* INPUT : wl_0_10
* INPUT : wl_0_11
* INPUT : wl_0_12
* INPUT : wl_0_13
* INPUT : wl_0_14
* INPUT : wl_0_15
* POWER : vdd
* GROUND: gnd
* rbl: [1, 0] left_rbl: [0] right_rbl: []
Xreplica_bitcell_array
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 rbl_wl_0_0 wl_0_0 wl_0_1 wl_0_2
+ wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11
+ wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd
+ sram_replica_bitcell_array
Xdummy_row_bot
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 gnd vdd gnd
+ sram_dummy_array_1
Xdummy_row_top
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 gnd vdd gnd
+ sram_dummy_array_0
Xdummy_col_left
+ dummy_left_bl_0_0 dummy_left_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1
+ wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10
+ wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd
+ sram_dummy_array_2
Xdummy_col_right
+ dummy_right_bl_0_0 dummy_right_br_0_0 gnd rbl_wl_0_0 wl_0_0 wl_0_1
+ wl_0_2 wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10
+ wl_0_11 wl_0_12 wl_0_13 wl_0_14 wl_0_15 gnd vdd gnd
+ sram_dummy_array_3
.ENDS sram_capped_replica_bitcell_array
.SUBCKT sram_bank
+ dout0_0 rbl_bl_0_0 din0_0 addr0_0 addr0_1 addr0_2 addr0_3 s_en0
+ p_en_bar0 w_en0 wl_en0 vdd gnd
* OUTPUT: dout0_0
* OUTPUT: rbl_bl_0_0
* INPUT : din0_0
* INPUT : addr0_0
* INPUT : addr0_1
* INPUT : addr0_2
* INPUT : addr0_3
* INPUT : s_en0
* INPUT : p_en_bar0
* INPUT : w_en0
* INPUT : wl_en0
* POWER : vdd
* GROUND: gnd
Xbitcell_array
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 rbl_wl0 wl_0_0 wl_0_1 wl_0_2
+ wl_0_3 wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11
+ wl_0_12 wl_0_13 wl_0_14 wl_0_15 vdd gnd
+ sram_capped_replica_bitcell_array
Xport_data0
+ rbl_bl_0_0 rbl_br_0_0 bl_0_0 br_0_0 dout0_0 din0_0 s_en0 p_en_bar0
+ w_en0 vdd gnd
+ sram_port_data
Xport_address0
+ addr0_0 addr0_1 addr0_2 addr0_3 wl_en0 wl_0_0 wl_0_1 wl_0_2 wl_0_3
+ wl_0_4 wl_0_5 wl_0_6 wl_0_7 wl_0_8 wl_0_9 wl_0_10 wl_0_11 wl_0_12
+ wl_0_13 wl_0_14 wl_0_15 rbl_wl0 vdd gnd
+ sram_port_address
.ENDS sram_bank
.SUBCKT sram_row_addr_dff
+ din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd
* INPUT : din_0
* INPUT : din_1
* INPUT : din_2
* INPUT : din_3
* OUTPUT: dout_0
* OUTPUT: dout_1
* OUTPUT: dout_2
* OUTPUT: dout_3
* INPUT : clk
* POWER : vdd
* GROUND: gnd
* rows: 4 cols: 1
Xdff_r0_c0
+ din_0 dout_0 clk vdd gnd
+ dff
Xdff_r1_c0
+ din_1 dout_1 clk vdd gnd
+ dff
Xdff_r2_c0
+ din_2 dout_2 clk vdd gnd
+ dff
Xdff_r3_c0
+ din_3 dout_3 clk vdd gnd
+ dff
.ENDS sram_row_addr_dff
.SUBCKT sram_data_dff
+ din_0 dout_0 clk vdd gnd
* INPUT : din_0
* OUTPUT: dout_0
* INPUT : clk
* POWER : vdd
* GROUND: gnd
* rows: 1 cols: 1
Xdff_r0_c0
+ din_0 dout_0 clk vdd gnd
+ dff
.ENDS sram_data_dff
.SUBCKT sram
+ din0[0] addr0[0] addr0[1] addr0[2] addr0[3] csb0 web0 clk0 dout0[0]
+ vdd gnd
* INPUT : din0[0]
* INPUT : addr0[0]
* INPUT : addr0[1]
* INPUT : addr0[2]
* INPUT : addr0[3]
* INPUT : csb0
* INPUT : web0
* INPUT : clk0
* OUTPUT: dout0[0]
* POWER : vdd
* GROUND: gnd
Xbank0
+ dout0[0] rbl_bl0 bank_din0_0 a0_0 a0_1 a0_2 a0_3 s_en0 p_en_bar0 w_en0
+ wl_en0 vdd gnd
+ sram_bank
Xcontrol0
+ csb0 web0 clk0 rbl_bl0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd
+ sram_control_logic_rw
Xrow_address0
+ addr0[0] addr0[1] addr0[2] addr0[3] a0_0 a0_1 a0_2 a0_3 clk_buf0 vdd
+ gnd
+ sram_row_addr_dff
Xdata_dff0
+ din0[0] bank_din0_0 clk_buf0 vdd gnd
+ sram_data_dff
.ENDS sram