mirror of https://github.com/VLSIDA/OpenRAM.git
62 lines
2.3 KiB
Python
62 lines
2.3 KiB
Python
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import sram_config
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class fake_sram(sram_config.sram_config):
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""" This is an SRAM that doesn't actually create itself, just computes
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the sizes. """
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def __init__(self, word_size, num_words, num_banks, name, num_spare_rows):
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self.name = name
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self.word_size = word_size
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self.num_words = num_words
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self.num_banks = num_banks
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self.num_spare_rows = num_spare_rows
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# TODO: Get width and height from gds bbox
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self.width = 0
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self.height = 0
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#c = reload(__import__(OPTS.bitcell))
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#self.mod_bitcell = getattr(c, OPTS.bitcell)
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#self.bitcell = self.mod_bitcell()
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# to get the row, col, etc.
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self.compute_sizes()
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self.setup_multiport_constants()
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def setup_multiport_constants(self):
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"""
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Taken from ../base/design.py
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These are contants and lists that aid multiport design.
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Ports are always in the order RW, W, R.
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Port indices start from 0 and increment.
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A first RW port will have clk0, csb0, web0, addr0, data0
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A first W port (with no RW ports) will be: clk0, csb0, addr0, data0
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"""
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total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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# These are the read/write port indices.
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self.readwrite_ports = []
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# These are the read/write and write-only port indices
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self.write_ports = []
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# These are the write-only port indices.
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self.writeonly_ports = []
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# These are the read/write and read-only port indices
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self.read_ports = []
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# These are the read-only port indices.
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self.readonly_ports = []
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# These are all the ports
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self.all_ports = list(range(total_ports))
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# The order is always fixed as RW, W, R
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port_number = 0
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for port in range(OPTS.num_rw_ports):
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self.readwrite_ports.append(port_number)
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self.write_ports.append(port_number)
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self.read_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_w_ports):
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self.write_ports.append(port_number)
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self.writeonly_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_r_ports):
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self.read_ports.append(port_number)
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self.readonly_ports.append(port_number)
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port_number += 1
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