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OpenRAM/compiler/tests/03_wire_test.py

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Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.
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#!/usr/bin/env python3
"Run a regression test on a basic wire"
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import unittest
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from testutils import header,openram_test
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import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
Update unit tests to load verify after config file. Start magic DRC.
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from globals import OPTS
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import debug
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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class wire_test(openram_test):
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def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import wire
import tech
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import design
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min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("poly", "contact", "metal1")
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old_position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
w = design.design("wire_test1")
wire.wire(w, layer_stack, position_list)
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_poly"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "contact", "poly")
Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.
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old_position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
w = design.design("wire_test2")
wire.wire(w, layer_stack, position_list)
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal1", "via1", "metal2")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.
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w = design.design("wire_test3")
wire.wire(w, layer_stack, position_list)
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal1"])
layer_stack = ("metal2", "via1", "metal1")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.
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w = design.design("wire_test4")
wire.wire(w, layer_stack, position_list)
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal2", "via2", "metal3")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list.reverse()
Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.
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w = design.design("wire_test5")
wire.wire(w, layer_stack, position_list)
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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self.local_drc_check(w)
RELEASE 1.0
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min_space = 2 * (tech.drc["minwidth_metal2"] +
tech.drc["minwidth_metal3"])
layer_stack = ("metal3", "via2", "metal2")
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list.reverse()
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w = design.design("wire_test6")
wire.wire(w, layer_stack, position_list)
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
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self.local_drc_check(w)
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Remove openram_temp at end of openram and unit tests.
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()