mirror of https://github.com/VLSIDA/OpenRAM.git
25 lines
780 B
Python
25 lines
780 B
Python
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word_size = 32
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num_words = 512
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write_size = 8
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num_rw_ports = 1
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num_r_ports = 1
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num_w_ports = 0
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tech_name = "scn4m_subm"
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nominal_corners_only = True
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route_supplies = True
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check_lvsdrc = True
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perimeter_pins = True
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#netlist_only = True
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#analytical_delay = False
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output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
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num_words,
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write_size,
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tech_name)
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output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
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num_words,
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write_size,
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tech_name)
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