mirror of https://github.com/VLSIDA/OpenRAM.git
24 lines
707 B
Python
24 lines
707 B
Python
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import design
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import debug
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import utils
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from tech import GDS,layer
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class sense_amp(design.design):
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"""
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This module implements the single sense amp cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library.
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Sense amplifier to read a pair of bit-lines.
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"""
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pins = ["BL", "BR", "Dout", "SCLK", "vdd", "gnd"]
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chars = utils.auto_measure_libcell(pins, "sense_amp", GDS["unit"], layer["boundary"])
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def __init__(self, name):
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design.design.__init__(self, name)
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debug.info(2, "Create Sense Amp object")
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self.width = sense_amp.chars["width"]
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self.height = sense_amp.chars["height"]
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