mirror of https://github.com/VLSIDA/OpenRAM.git
82 lines
3.0 KiB
Python
82 lines
3.0 KiB
Python
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import debug
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import design
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from tech import drc, spice
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from vector import vector
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from globals import OPTS
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from pbitcell import pbitcell
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class replica_pbitcell(design.design):
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"""
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Creates a replica bitcell using pbitcell
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"""
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def __init__(self):
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self.num_rw_ports = OPTS.num_rw_ports
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self.num_w_ports = OPTS.num_w_ports
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self.num_r_ports = OPTS.num_r_ports
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self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
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design.design.__init__(self, "replica_pbitcell")
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debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
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self.num_w_ports,
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self.num_r_ports))
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_modules()
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def create_layout(self):
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self.place_pbitcell()
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self.route_rbc_connections()
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self.DRC_LVS()
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def add_pins(self):
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for port in range(self.total_ports):
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self.add_pin("bl{}".format(port))
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self.add_pin("br{}".format(port))
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for port in range(self.total_ports):
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self.add_pin("wl{}".format(port))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.prbc = pbitcell(replica_bitcell=True)
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self.add_mod(self.prbc)
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self.height = self.prbc.height
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self.width = self.prbc.width
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def create_modules(self):
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self.prbc_inst = self.add_inst(name="pbitcell",
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mod=self.prbc)
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temp = []
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for port in range(self.total_ports):
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temp.append("bl{}".format(port))
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temp.append("br{}".format(port))
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for port in range(self.total_ports):
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temp.append("wl{}".format(port))
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def place_pbitcell(self):
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offset = [0,0]
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self.prbc_inst.place(offset=offset)
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def route_rbc_connections(self):
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for port in range(self.total_ports):
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self.copy_layout_pin(self.prbc_inst, "bl{}".format(port))
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self.copy_layout_pin(self.prbc_inst, "br{}".format(port))
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for port in range(self.total_ports):
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self.copy_layout_pin(self.prbc_inst, "wl{}".format(port))
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self.copy_layout_pin(self.prbc_inst, "vdd")
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self.copy_layout_pin(self.prbc_inst, "gnd")
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