mirror of https://github.com/VLSIDA/OpenRAM.git
124 lines
4.7 KiB
Python
124 lines
4.7 KiB
Python
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#!/usr/bin/env python3
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"""
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Datasheet Generator
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TODO:
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locate all port elements in .lib
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Locate all timing elements in .lib
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Diagram generation
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Improve css
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"""
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import os, math
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import optparse
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from flask_table import *
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import csv
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from globals import OPTS
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from deliverables import *
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from operating_conditions import *
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from timing_and_current_data import *
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from characterization_corners import *
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from datasheet import *
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def process_name(corner):
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if corner == "TT":
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return "Typical - Typical"
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if corner == "SS":
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return "Slow - Slow"
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if corner == "FF":
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return "Fast - Fast"
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else:
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return "custom"
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def parse_file(f,pages):
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with open(f) as csv_file:
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csv_reader = csv.reader(csv_file, delimiter=',')
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line_count = 0
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for row in csv_reader:
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found = 0
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NAME = row[0]
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NUM_WORDS = row[1]
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NUM_BANKS = row[2]
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NUM_RW_PORTS = row[3]
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NUM_W_PORTS = row[4]
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NUM_R_PORTS = row[5]
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TECH_NAME = row[6]
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TEMP = row[7]
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VOLT = row[8]
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PROC = row[9]
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MIN_PERIOD = row[10]
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OUT_DIR = row[11]
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LIB_NAME = row[12]
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for sheet in pages:
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if sheet.name == row[0]:
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found = 1
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#if the .lib information is for an existing datasheet compare timing data
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for item in sheet.operating:
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if item.parameter == 'Operating Temperature':
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if float(TEMP) > float(item.max):
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item.typ = item.max
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item.max = TEMP
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if float(TEMP) < float(item.min):
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item.typ = item.min
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item.min = TEMP
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if item.parameter == 'Power supply (VDD) range':
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if float(VOLT) > float(item.max):
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item.typ = item.max
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item.max = VOLT
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if float(VOLT) < float(item.min):
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item.typ = item.min
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item.min = VOLT
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if item.parameter == 'Operating Frequncy (F)':
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if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)):
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item.max = str(math.floor(1000/float(MIN_PERIOD)))
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new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
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new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
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if found == 0:
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new_sheet = datasheet(NAME)
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pages.append(new_sheet)
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new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
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new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'))
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new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius'))
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new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'))
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new_sheet.timing.append(timing_and_current_data_item('1','2','3','4'))
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new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'sp')))
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new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'v')))
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new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'gds')))
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new_sheet.dlv.append(deliverables_item('.lef','LEF files','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'lef')))
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new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
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class parse():
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def __init__(self,in_dir,out_dir):
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if not (os.path.isdir(in_dir)):
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os.mkdir(in_dir)
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if not (os.path.isdir(out_dir)):
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os.mkdir(out_dir)
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datasheets = []
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parse_file(in_dir + "/datasheet.info", datasheets)
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for sheets in datasheets:
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# print (out_dir + sheets.name + ".html")
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with open(out_dir + "/" + sheets.name + ".html", 'w+') as f:
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sheets.generate_html()
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f.write(sheets.html)
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