mirror of https://github.com/VLSIDA/OpenRAM.git
36 lines
772 B
Python
36 lines
772 B
Python
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from drc_value import *
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from drc_lut import *
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class design_rules():
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"""
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This is a class that implements the design rules structures.
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"""
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def __init__(self, name):
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self.tech_name = name
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self.rules = {}
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def add(self, name, value):
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self.rules[name] = value
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def __call__(self, name, *args):
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return self.rules[name](args)
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def __setitem__(self, b, c):
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"""
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For backward compatibility with existing rules.
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"""
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self.rules[b] = c
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def __getitem__(self, b):
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"""
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For backward compatibility with existing rules.
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"""
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rule = self.rules[b]
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if callable(rule):
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return rule()
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else:
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return rule
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