mirror of https://github.com/VLSIDA/OpenRAM.git
37 lines
626 B
Coq
37 lines
626 B
Coq
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module multibank # (
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DATA_WIDTH = 32,
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ADDR_WIDTH= 8
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)(
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#<RW_PORTS
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clk#$PORT_NUM$#,
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addr#$PORT_NUM$#,
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din#$PORT_NUM$#,
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csb#$PORT_NUM$#,
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web#$PORT_NUM$#,
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dout#$PORT_NUM$#,
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#>RW_PORTS
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#<R_PORTS
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clk#$PORT_NUM$#,
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addr#$PORT_NUM$#,
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csb#$PORT_NUM$#,
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web#$PORT_NUM$#,
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dout#$PORT_NUM$#,
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#>R_PORTS
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);
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parameter RAM_DEPTH = 1 << ADRR_WIDTH;
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#<BANK_INIT
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bank bank#$BANK_NUM$# #(DATA_WIDTH, ADDR_WIDTH) (
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#<BANK_RW_PORTS
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clk#$PORT_NUM$#,
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addr#$PORT_NUM$#,
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din#$PORT_NUM$#,
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csb#$PORT_NUM$#,
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web#$PORT_NUM$#,
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dout#$PORT_NUM$#,
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#>BANK_R_PORTS
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)
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#>BANK_INIT
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