2016-11-08 18:57:35 +01:00
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import sys
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import re
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import globals
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import debug
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import tech
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import math
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import stimuli
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import charutils as ch
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2016-11-11 18:41:43 +01:00
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import utils
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2016-11-08 18:57:35 +01:00
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OPTS = globals.get_opts()
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class delay():
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"""
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Functions to measure the delay of the SRAM at a given address and
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data bit.
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"""
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def __init__(self,sram,spfile):
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self.name = sram.name
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self.num_words = sram.num_words
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self.word_size = sram.word_size
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self.addr_size = sram.addr_size
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self.sram_sp_file = spfile
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def check_arguments(self):
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"""Checks if arguments given for write_stimulus() meets requirements"""
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try:
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int(self.probe_address, 2)
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except ValueError:
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debug.error("Probe Address is not of binary form: {0}".format(self.probe_address),1)
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if len(self.probe_address) != self.addr_size:
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debug.error("Probe Address's number of bits does not correspond to given SRAM",1)
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if not isinstance(self.probe_data, int) or self.probe_data>self.word_size or self.probe_data<0:
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debug.error("Given probe_data is not an integer to specify a data bit",1)
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def write_stimulus(self, feasible_period, target_period, data_value):
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"""Creates a stimulus file for simulations to probe a certain bitcell, given an address and data-position of the data-word
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(probe-address form: '111010000' LSB=0, MSB=1)
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(probe_data form: number corresponding to the bit position of data-bus, begins with position 0)
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"""
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self.check_arguments()
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# obtains list of time-points for each rising clk edge
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self.obtain_cycle_times(slow_period=feasible_period,
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fast_period=target_period)
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# creates and opens stimulus file for writing
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Stimulus data value of {0} for target period of {1}n\n".format(data_value, target_period))
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self.sf.write("\n")
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# include files in stimulus file
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model_list = tech.spice["fet_models"] + [self.sram_sp_file]
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stimuli.write_include(stim_file=self.sf, models=model_list)
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self.sf.write("\n")
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# add vdd/gnd statements
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self.sf.write("* Global Power Supplies\n")
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stimuli.write_supply(stim_file=self.sf,
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vdd_name=tech.spice["vdd_name"],
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gnd_name=tech.spice["gnd_name"],
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vdd_voltage=tech.spice["supply_voltage"],
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gnd_voltage=tech.spice["gnd_voltage"])
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self.sf.write("\n")
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# instantiate the sram
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self.sf.write("* Instantiation of the SRAM\n")
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stimuli.inst_sram(stim_file=self.sf,
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abits=self.addr_size,
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dbits=self.word_size,
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sram_name=self.name)
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self.sf.write("\n")
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# create a buffer and an inverter
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self.sf.write("* Buffers and inverter Initialization\n")
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# FIXME: We should replace the clock buffer with the same
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# 2x buffer for control signals. This needs the buffer to be
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# added to the control logic though.
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stimuli.create_buffer(stim_file=self.sf,
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buffer_name="clk1_buffer",
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size=[1, 4])
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self.sf.write("\n")
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stimuli.create_buffer(stim_file=self.sf,
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buffer_name="clk2_buffer",
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size=[8, 16])
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self.sf.write("\n")
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stimuli.create_buffer(stim_file=self.sf,
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buffer_name="buffer",
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size=[1, 2])
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self.sf.write("\n")
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stimuli.create_inverter(stim_file=self.sf)
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self.sf.write("\n")
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# add a buffer for each signal and an inverter for WEb
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signal_list = []
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for i in range(self.word_size):
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signal_list.append("D[{0}]".format(i))
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for j in range(self.addr_size):
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signal_list.append("A[{0}]".format(j))
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for k in tech.spice["control_signals"]:
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signal_list.append(k)
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self.sf.write("*Buffers for each generated signal and Inv for WEb\n")
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stimuli.add_buffer(stim_file=self.sf,
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buffer_name="buffer",
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signal_list=signal_list)
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stimuli.add_buffer(stim_file=self.sf,
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buffer_name="clk1_buffer",
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signal_list=["clk"])
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stimuli.add_buffer(stim_file=self.sf,
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buffer_name="clk2_buffer",
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signal_list=["clk_buf"])
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stimuli.add_buffer(stim_file=self.sf,
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buffer_name="buffer",
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signal_list=["WEb_trans"])
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stimuli.add_inverter(stim_file=self.sf,
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signal_list=["WEb_trans"])
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self.sf.write("\n")
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# add access transistors for data-bus
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self.sf.write("* Transmission Gates for data-bus\n")
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stimuli.add_accesstx(stim_file=self.sf, dbits=self.word_size)
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self.sf.write("\n")
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# generate data and addr signals
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self.sf.write("*Generation of data and address signals\n")
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if data_value == tech.spice["supply_voltage"]:
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v_val = tech.spice["gnd_voltage"]
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else:
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v_val = tech.spice["supply_voltage"]
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for i in range(self.word_size):
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if i == self.probe_data:
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stimuli.gen_data_pwl(stim_file=self.sf,
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key_times=self.cycle_times,
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sig_name="D[{0}]".format(i),
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data_value=data_value,
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feasible_period=feasible_period,
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target_period=target_period,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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else:
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stimuli.gen_constant(stim_file=self.sf,
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sig_name="D[{0}]".format(i),
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v_ref=tech.spice["gnd_voltage"],
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v_val=v_val)
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stimuli.gen_addr_pwl(stim_file=self.sf,
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key_times=self.cycle_times,
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addr=self.probe_address,
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feasible_period=feasible_period,
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target_period=target_period,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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self.sf.write("\n")
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# generate control signals
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self.sf.write("*Generation of control signals\n")
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# CSb
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(x_list, y_list) = stimuli.gen_csb_pwl(key_times=self.cycle_times,
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feasible_period=feasible_period,
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target_period=target_period,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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stimuli.gen_pwl(stim_file=self.sf,
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sig_name="CSb",
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x_list=x_list,
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y_list=y_list)
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# WEb
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(x_list, y_list) = stimuli.gen_web_pwl(key_times=self.cycle_times,
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feasible_period=feasible_period,
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target_period=target_period,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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stimuli.gen_pwl(stim_file=self.sf,
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sig_name="WEb",
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x_list=x_list,
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y_list=y_list)
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# OEb
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(x_list, y_list) = stimuli.gen_oeb_pwl(key_times=self.cycle_times,
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feasible_period=feasible_period,
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target_period=target_period,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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stimuli.gen_pwl(stim_file=self.sf,
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sig_name="OEb",
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x_list=x_list,
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y_list=y_list)
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# WEb_transmission_gate
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(x_list, y_list) = stimuli.gen_web_trans_pwl(key_times=self.cycle_times,
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feasible_period=feasible_period,
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target_period=target_period,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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stimuli.gen_pwl(stim_file=self.sf,
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sig_name="WEb_trans",
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x_list=x_list,
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y_list=y_list)
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self.sf.write("\n")
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self.write_clock()
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self.write_measures(data_value)
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self.write_control()
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self.sf.close()
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def write_clock(self):
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# generate clk PWL based on the clock periods
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self.sf.write("* Generation of global clock signal\n")
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stimuli.gen_clk_pwl(stim_file=self.sf,
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cycle_times=self.cycle_times,
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t_rise=tech.spice["rise_time"],
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t_fall=tech.spice["fall_time"])
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self.sf.write("\n")
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def write_measures(self, data_value):
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# meas statement for delay and power measurements
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self.sf.write("* Measure statements for delay and power\n")
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# add measure statments for delay
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trig_name = tech.spice["clk"] + "_buf_buf"
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targ_name = "{0}".format("DATA[{0}]".format(self.probe_data))
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trig_val = targ_val = 0.5 * tech.spice["supply_voltage"]
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trig_dir = self.read_cycle
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targ_dir = "RISE" if data_value == tech.spice["supply_voltage"] else "FALL"
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td = self.cycle_times[self.clear_bus_cycle]
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stimuli.gen_meas_delay(stim_file=self.sf,
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meas_name="DELAY",
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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targ_val=targ_val,
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trig_dir=trig_dir,
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targ_dir=targ_dir,
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td=td)
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# add measure statements for power
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t_initial = self.cycle_times[self.write_cycle]
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t_final = self.cycle_times[self.write_cycle+1]
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stimuli.gen_meas_power(stim_file=self.sf,
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meas_name="POWER_WRITE",
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.read_cycle]
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t_final = self.cycle_times[self.read_cycle+1]
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stimuli.gen_meas_power(stim_file=self.sf,
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meas_name="POWER_READ",
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t_initial=t_initial,
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t_final=t_final)
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self.sf.write("\n")
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def write_control(self):
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# run until the last cycle time
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end_time = self.cycle_times[-1]
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self.sf.write(".TRAN 5p {0}n\n".format(end_time))
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if OPTS.spice_version == "hspice":
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# create plots for all signals
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self.sf.write(".OPTIONS POST=1 PROBE\n")
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self.sf.write(".probe V(*)\n")
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# end the stimulus file
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self.sf.write(".end\n")
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self.sf.close()
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else:
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self.sf.write(".control\n")
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self.sf.write("run\n")
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self.sf.write("quit\n")
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self.sf.write(".endc\n")
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self.sf.write(".end\n")
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def find_feasible_period(self,initial_period):
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"""Uses an initial period and finds a feasible period before we
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run the binary search algorithm to find min period. We check if
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the given clock period is valid and if it's not, we continue to
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double the period until we find a valid period to use as a
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starting point. """
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feasible_period = initial_period
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time_out = 8
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while True:
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debug.info(1, "Finding feasible period: {0}ns".format(feasible_period))
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time_out -= 1
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if (time_out <= 0):
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debug.error("Timed out, could not find a feasible period.",2)
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(success, delay_out)=self.try_period(feasible_period,feasible_period,tech.spice["supply_voltage"])
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if not success:
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feasible_period = 2 * feasible_period
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continue
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(success, delay_out)=self.try_period(feasible_period,feasible_period,tech.spice["gnd_voltage"])
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if not success:
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feasible_period = 2 * feasible_period
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continue
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debug.info(1, "Starting Binary Search Algorithm with feasible_period: {0}ns".format(feasible_period))
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return feasible_period
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def try_period(self, feasible_period, target_period, data_value):
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""" This tries to simulate a period and checks if the result
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|
works. If so, it returns True. If not, it it doubles the
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period and returns False."""
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# Checking from not data_value to data_value
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self.write_stimulus(feasible_period, target_period, data_value)
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stimuli.run_sim()
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delay_value = ch.convert_to_float(ch.parse_output("timing", "delay"))
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# if it failed or the read was longer than a period
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if type(delay_value)!=float or delay_value*1e9>target_period:
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debug.info(2,"Infeasible period " + str(target_period) + " delay " + str(delay_value*1e9) + "ns")
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return (False, "NA")
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else:
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debug.info(2,"Feasible period " + str(feasible_period) \
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|
+ ", target period " + str(target_period) \
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|
+ ", read/write of " + str(data_value) \
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+ ", delay=" + str(delay_value*1e9) + "ns")
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#key=raw_input("press return to continue")
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return (True, delay_value*1e9)
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def find_min_period(self,data_value):
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|
"""Creates a spice test and instantiates a single SRAM for
|
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|
testing. Returns a tuple of the lowest period and its
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|
|
|
clk-to-q delay for the specified data_value."""
|
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|
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|
|
# Find a valid and feasible period before starting the binary search
|
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|
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|
# We just try 2.0ns here, but any value would work albeit slower.
|
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|
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|
feasible_period = self.find_feasible_period(tech.spice["feasible_period"])
|
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|
|
previous_period = ub_period = feasible_period
|
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|
|
lb_period = 0.0
|
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|
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|
|
|
|
# Binary search algorithm to find the min period (max frequency) of design
|
|
|
|
|
time_out = 25
|
|
|
|
|
while True:
|
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|
|
|
time_out -= 1
|
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|
|
|
if (time_out <= 0):
|
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|
|
debug.error("Timed out, could not converge on minimum period.",2)
|
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|
|
|
|
|
|
|
|
target_period = 0.5 * (ub_period + lb_period)
|
|
|
|
|
debug.info(1, "MinPeriod Search: {0}ns (ub: {1} lb: {2})".format(target_period,
|
|
|
|
|
ub_period,
|
|
|
|
|
lb_period))
|
|
|
|
|
|
|
|
|
|
(success, delay_out) = self.try_period(feasible_period, target_period, data_value)
|
|
|
|
|
if success:
|
|
|
|
|
if ch.relative_compare(ub_period, target_period):
|
|
|
|
|
# use the two values to compare, but only return the ub since it is guaranteed feasible
|
|
|
|
|
(success, delay_out) = self.try_period(feasible_period, ub_period, data_value)
|
|
|
|
|
return (ub_period, delay_out)
|
|
|
|
|
fail_flag = False
|
|
|
|
|
ub_period = target_period
|
|
|
|
|
else:
|
|
|
|
|
lb_period = target_period
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
self.error("Should not reach here.",-1)
|
|
|
|
|
return (target_period, delay_out)
|
|
|
|
|
|
|
|
|
|
def set_probe(self,probe_address, probe_data):
|
|
|
|
|
""" Probe address and data can be set separately to utilize other
|
|
|
|
|
functions in this characterizer besides analyze."""
|
|
|
|
|
self.probe_address = probe_address
|
|
|
|
|
self.probe_data = probe_data
|
|
|
|
|
|
|
|
|
|
def analyze(self,probe_address, probe_data):
|
|
|
|
|
"""main function to calculate the min period for a low_to_high
|
|
|
|
|
transistion and a high_to_low transistion returns a dictionary
|
|
|
|
|
that contains all both the min period and associated delays
|
|
|
|
|
Dictionary Keys: min_period1, delay1, min_period0, delay0
|
|
|
|
|
"""
|
|
|
|
|
self.set_probe(probe_address, probe_data)
|
|
|
|
|
|
|
|
|
|
(min_period1, delay1) = self.find_min_period(tech.spice["supply_voltage"])
|
|
|
|
|
if (min_period1 == None) or (delay1 == None):
|
|
|
|
|
return None
|
|
|
|
|
debug.info(1, "Min Period for low_to_high transistion: {0}n with a delay of {1}".format(min_period1, delay1))
|
|
|
|
|
(min_period0, delay0) = self.find_min_period(tech.spice["gnd_voltage"])
|
|
|
|
|
if (min_period0 == None) or (delay0 == None):
|
|
|
|
|
return None
|
|
|
|
|
debug.info(1, "Min Period for high_to_low transistion: {0}n with a delay of {1}".format(min_period0, delay0))
|
|
|
|
|
data = {"min_period1": min_period1, # period in ns
|
|
|
|
|
"delay1": delay1, # delay in s
|
|
|
|
|
"min_period0": min_period0,
|
|
|
|
|
"delay0": delay0
|
|
|
|
|
}
|
|
|
|
|
return data
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
def obtain_cycle_times(self, slow_period, fast_period):
|
|
|
|
|
"""Returns a list of key time-points [ns] of the waveform (each rising edge)
|
|
|
|
|
of the cycles to do a timing evaluation. The last time is the end of the simulation
|
|
|
|
|
and does not need a rising edge."""
|
|
|
|
|
|
|
|
|
|
# idle: half cycle, no operation
|
|
|
|
|
t_current = 0.5 * slow_period
|
|
|
|
|
|
|
|
|
|
# slow cycle1: W data 1 address 1111 to initialize cell to a value
|
|
|
|
|
self.cycle_times = [t_current]
|
|
|
|
|
self.init_cycle=1
|
|
|
|
|
t_current += slow_period
|
|
|
|
|
|
|
|
|
|
# slow cycle2: R data 1 address 1111 (to ensure cell was written to opposite data value)
|
|
|
|
|
self.cycle_times.append(t_current)
|
|
|
|
|
self.verify_init_cycle=2
|
|
|
|
|
t_current += slow_period
|
|
|
|
|
|
|
|
|
|
# fast cycle3: W data 0 address 1111 (to ensure a write of opposite value works)
|
|
|
|
|
self.cycle_times.append(t_current)
|
|
|
|
|
self.write_cycle=3
|
|
|
|
|
t_current += fast_period
|
|
|
|
|
|
|
|
|
|
# fast cycle4: W data 1 address 0000 (to invert the bus cap from prev write)
|
|
|
|
|
self.cycle_times.append(t_current)
|
|
|
|
|
self.clear_bus_cycle=4
|
|
|
|
|
t_current += fast_period
|
|
|
|
|
|
|
|
|
|
# fast cycle5: R data 0 address 1111 (to ensure that a read works and gets the value)
|
|
|
|
|
self.cycle_times.append(t_current)
|
|
|
|
|
self.read_cycle=5
|
|
|
|
|
t_current += fast_period
|
|
|
|
|
|
|
|
|
|
# slow cycle 6: wait a slow clock period to end the simulation
|
|
|
|
|
self.cycle_times.append(t_current)
|
|
|
|
|
self.wait_cycle=6
|
|
|
|
|
t_current += slow_period
|
|
|
|
|
|
|
|
|
|
# end time of simulation
|
|
|
|
|
self.cycle_times.append(t_current)
|
|
|
|
|
|
