mirror of https://github.com/VLSIDA/OpenRAM.git
225 lines
10 KiB
Python
225 lines
10 KiB
Python
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import design
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import debug
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from tech import drc, cell
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from vector import vector
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from contact import contact
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from ptx import ptx
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from globals import OPTS
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class single_level_column_mux(design.design):
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"""
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This module implements the columnmux bitline cell used in the design.
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Creates a single columnmux cell.
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"""
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def __init__(self, name, tx_size):
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design.design.__init__(self, name)
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debug.info(2, "create single columnmux cell: {0}".format(name))
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c = reload(__import__(OPTS.config.bitcell))
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self.mod_bitcell = getattr(c, OPTS.config.bitcell)
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self.bitcell_chars = self.mod_bitcell.chars
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self.tx_size = tx_size
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self.ptx_width = self.tx_size * drc["minwidth_tx"]
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self.add_pins()
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self.create_layout()
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def add_pins(self):
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self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"])
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def create_layout(self):
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# This is not instantiated and used for calculations only.
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self.m1m2_via = contact(layer_stack=("metal1", "via1", "metal2"))
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self.pwell_contact = contact(layer_stack=("active", "contact", "metal1"))
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self.create_ptx()
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self.add_ptx()
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self.connect_poly()
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self.connect_to_bitlines()
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self.add_gnd_rail()
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self.add_well_contacts()
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self.setup_layout_constants()
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def create_ptx(self):
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"""Initializes the nmos1 and nmos2 transistors"""
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self.nmos1 = ptx(name="nmos1",
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width=self.ptx_width,
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mults=1,
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tx_type="nmos")
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self.add_mod(self.nmos1)
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self.nmos2 = ptx(name="nmos2",
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width=self.ptx_width,
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mults=1,
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tx_type="nmos")
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self.nmos2 = self.nmos2
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self.add_mod(self.nmos2)
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def add_ptx(self):
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# Adds nmos1,nmos2 to the module
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self.nmos1_position = (vector(drc["minwidth_metal1"],
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drc["poly_extend_active"])
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- vector([drc["well_enclosure_active"]]*2))
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self.add_inst(name="M_1",
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mod=self.nmos1,
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offset=self.nmos1_position)
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self.connect_inst(["bl", "sel", "bl_out", "gnd"])
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nmos2_to_nmos1 = vector(self.nmos1.active_width,
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self.nmos1.active_height + drc["minwidth_poly"]
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+ 2* drc["poly_extend_active"])
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self.nmos2_position = self.nmos1_position + nmos2_to_nmos1
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self.add_inst(name="M_2",
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mod=self.nmos2,
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offset=self.nmos2_position)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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def connect_poly(self):
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self.poly_offset = (self.nmos1_position
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+ self.nmos1.poly_positions[0]
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+ vector(0,self.nmos1.poly_height))
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width=self.nmos2_position[0] - self.nmos1_position[0] + drc["minwidth_poly"]
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self.poly = self.add_rect(layer="poly",
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offset=self.poly_offset,
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width=width,
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height=drc["minwidth_poly"])
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self.add_label(text="col_addr",
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layer="poly",
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offset=self.poly_offset)
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def connect_to_bitlines(self):
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offset = [self.nmos1.active_contact_positions[0].x + self.m1m2_via.contact_width / 2
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+ 3 * (self.m1m2_via.second_layer_width - self.m1m2_via.first_layer_width) / 2,
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self.nmos1.active_position[1] + self.nmos1.active_height]
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offset = self.nmos1_position + offset
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connection = vector(0,
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self.nmos2.active_height+ 2 * drc["poly_extend_active"] \
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+ drc["minwidth_poly"] + drc["minwidth_metal2"])
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self.add_rect(layer="metal2",
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offset=offset,
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width=drc["minwidth_metal2"],
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height=connection.y - drc["minwidth_metal2"])
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self.BL_position = (vector(self.bitcell_chars["BL"][0] - 0.5 * self.m1m2_via.width,
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offset.y)
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+ connection)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset,
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mirror="MX")
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self.add_label(text="bl",
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layer="metal2",
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offset=self.BL_position)
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self.add_rect(layer="metal2",
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offset=self.BL_position - vector(0, 2 * drc["minwidth_metal2"]),
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width=drc["minwidth_metal2"],
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height=2 * drc["minwidth_metal2"])
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width = self.bitcell_chars["BL"][0] - 0.5 * self.m1m2_via.width - offset[0] + drc["minwidth_metal2"]
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self.add_rect(layer="metal2",
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offset=[offset[0],
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self.BL_position[1] - 2*drc["minwidth_metal2"]],
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width=width,
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height=drc["minwidth_metal2"])
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offset = self.nmos1_position + self.nmos1.active_contact_positions[1]
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset)
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self.add_rect(layer="metal2",
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offset=[self.bitcell_chars["BL"][0] - 0.5 * self.m1m2_via.width,
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0],
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width=drc["minwidth_metal2"],
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height=(drc["minwidth_metal2"] + offset[1]))
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self.add_rect(layer="metal2",
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offset=[self.bitcell_chars["BL"][0] - 0.5 * self.m1m2_via.width,
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offset[1]],
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width=(offset[0] - self.bitcell_chars["BL"][0] - 0.5 * self.m1m2_via.width
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+ 2 * drc["minwidth_metal2"]),
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height=drc["minwidth_metal2"])
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self.BL_out_position = vector(self.bitcell_chars["BL"][0] - 0.5* self.m1m2_via.width,
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0)
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self.add_label(text="bl_out",
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layer="metal2",
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offset=self.BL_out_position)
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offset = [self.nmos2.active_contact_positions[1].x - self.m1m2_via.contact_width / 2,
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self.nmos2.active_position[1] + self.nmos2.active_height]
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offset = self.nmos2_position + offset
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset,
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mirror="MX")
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mid = offset + vector(drc["minwidth_metal2"],0)
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self.add_rect(layer="metal2",
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offset= mid,
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width= (self.bitcell_chars["BR"][0] - mid[0] + 0.5*self.m1m2_via.width),
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height=-drc["minwidth_metal2"])
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self.add_rect(layer="metal2",
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offset=[self.bitcell_chars["BR"][0] - 0.5*self.m1m2_via.width,
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offset[1] - drc["metal1_to_metal1"]],
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width=drc["minwidth_metal2"],
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height=2*drc["minwidth_metal2"])
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self.BR_position = vector(self.bitcell_chars["BR"][0] - 0.5 * self.m1m2_via.width,
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self.BL_position.y)
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self.add_label(text="br",
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layer="metal2",
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offset=self.BR_position)
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offset = self.nmos2_position + self.nmos2.active_contact_positions[0]
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self.BR_out_position = vector(self.bitcell_chars["BR"][0] - 0.5 * self.m1m2_via.width,
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0)
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self.add_label(text="br_out",
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layer="metal2",
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offset=self.BR_out_position)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset)
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self.add_rect(layer="metal2",
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offset=offset,
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width=self.BR_out_position.x - offset[0],
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height=drc["minwidth_metal2"])
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self.add_rect(layer="metal2",
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offset=[self.BR_out_position.x,
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offset[1] + drc["minwidth_metal2"]],
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width=drc["minwidth_metal2"],
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height=-(offset[1] + drc["minwidth_metal2"]))
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def add_gnd_rail(self):
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self.gnd_position = vector(self.bitcell_chars["gnd"][0] - 0.5 * self.m1m2_via.width,
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0)
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self.add_layout_pin(text="gnd",
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layer="metal2",
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offset=self.gnd_position,
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width=drc["minwidth_metal2"],
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height=self.BL_position[1])
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def add_well_contacts(self):
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offset = vector(self.gnd_position[0] + drc["minwidth_metal2"],
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self.nmos1.poly_height / 2)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset - vector(self.m1m2_via.width / 2, 0),
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mirror="MY")
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self.add_contact(layers=("active", "contact", "metal1"),
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offset=offset - vector(self.m1m2_via.width, 0),
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mirror="MY")
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temp = vector(self.m1m2_via.width,
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(self.pwell_contact.first_layer_height - self.pwell_contact.second_layer_height) / 2)
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offset_implant = offset - temp + vector([drc["implant_to_contact"]]*2).scale(1,-1)
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self.add_rect(layer="pimplant",
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offset=offset_implant,
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width=-(2*drc["implant_to_contact"] + self.pwell_contact.first_layer_width),
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height=2*drc["implant_to_contact"] + self.pwell_contact.width)
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offset_well = self.nmos1_position + vector(self.nmos1.width, 0)
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self.add_rect(layer="pwell",
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offset=offset_well,
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width=self.gnd_position[0] + drc["minwidth_metal2"] - offset_well[0],
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height=self.nmos1.height + drc["minwidth_poly"])
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self.add_rect(layer="vtg",
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offset=offset_well,
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width=self.gnd_position[0] + drc["minwidth_metal2"] - offset_well[0],
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height=self.nmos1.height + drc["minwidth_poly"])
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def setup_layout_constants(self):
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self.width = self.width = self.bitcell_chars["width"]
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self.height = self.height = self.BL_position[1]
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