OpenRAM/compiler/tests/10_write_driver_array_spare...

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#!/usr/bin/env python3
# See LICENSE for licensing information.
#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
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import sys, os
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import unittest
from testutils import *
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import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
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class write_driver_array_spare_cols_test(openram_test):
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def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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# check write driver array for single port
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debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3")
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a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3)
self.local_check(a)
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debug.info(2, "Testing write_driver_array for columns=16, word_size=8 and num_spare_cols=3")
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a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3)
self.local_check(a)
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# check write driver array for multi-port
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
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debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case and num_spare_cols=3")
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a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3)
self.local_check(a)
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debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case and num_spare_cols=3")
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a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3)
self.local_check(a)
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openram.end_openram()
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# run the test from the command line
if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())