Update PEX setup

.gitignore

@@ -15,7 +15,10 @@ modules/module_0_foundations/gmid_env
 *.npy
 *.so
 *.out
+*.nodes
+*.sim
 *.vcd
 *.npz
 *.log
 
+

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/pex_output/DIFF_COMPARATOR__DIFF_COMPARATOR/magic_RC/DIFF_COMPARATOR.ext

@@ -27,6 +27,12 @@ node "a_1245_3300#" 64 1432.03 1245 3300 pdif 0 0 0 0 646952 33468 462832 13040
 node "w_805_2869#" 1242572 5.18828 805 2869 pw 182658 17438 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 node "vdd" 58 17973.9 127 335 m6 0 0 0 0 2395440 52908 883744 19072 642880 13104 642880 13104 1340864 17360 6062752 36968 0 0
 substrate "gnd" 0 0 -513 -440 m7 0 0 0 0 2036008 30746 224000 4320 224000 4320 224000 4320 654400 6472 1331200 8256 9608000 48040
+cap "a_1245_3300#" "vdd" 2550.93
+cap "V+" "a_1245_3300#" 765.727
+cap "clk" "out-" 17.6324
+cap "a_1752_817#" "vdd" 7111.46
+cap "a_944_1911#" "vbias" 3.01856
+cap "clk" "a_687_2445#" 238.332
 cap "w_805_2869#" "out+" 7.86123
 cap "out-" "vbias" 0.0904886
 cap "a_1245_3300#" "a_944_1911#" 8045.22
@@ -42,8 +48,8 @@ cap "a_1245_3300#" "a_687_2445#" 11353.4
 cap "a_687_2445#" "a_1752_817#" 45.3073
 cap "a_944_1911#" "out+" 800.279
 cap "w_805_2869#" "a_944_1911#" 4.42903
-cap "clk" "vbias" 198.783
 cap "V+" "vdd" 4082.05
+cap "clk" "vbias" 198.783
 cap "V-" "out+" 9.67399
 cap "w_805_2869#" "V-" 10.604
 cap "out+" "out-" 93.2996
@@ -76,12 +82,6 @@ cap "a_1245_3300#" "out+" 369.238
 cap "w_805_2869#" "a_1245_3300#" 12.1813
 cap "vdd" "vbias" 2839.64
 cap "clk" "a_944_1911#" 247.428
-cap "a_1245_3300#" "vdd" 2550.93
-cap "V+" "a_1245_3300#" 765.727
-cap "clk" "out-" 17.6324
-cap "a_1752_817#" "vdd" 7111.46
-cap "a_944_1911#" "vbias" 3.01856
-cap "clk" "a_687_2445#" 238.332
 device msubckt sg13_lv_nmos 3710 1075 3711 1076 l=40 w=800 "gnd" "gnd" 80 0 "gnd" 0 0 "gnd" 1600 30400,876
 device msubckt sg13_lv_nmos 3594 1075 3595 1076 l=40 w=800 "gnd" "clk" 80 0 "a_944_1911#" 800 57600,944 "gnd" 800 30400,876
 device msubckt sg13_lv_nmos 3410 1075 3411 1076 l=40 w=800 "gnd" "a_687_2445#" 80 0 "gnd" 800 30400,876 "a_944_1911#" 800 57600,944

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/insert_pex_subckt.py

@@ -1,123 +0,0 @@
-import sys
-import os
-
-def load_text_file(file_path):
-    with open(file_path, 'r') as f:
-        return f.read()
-
-def save_text_file(file_path, text):
-    with open(file_path, 'w') as f:
-        f.write(text)
-
-def read_spice_definition(spice_path):
-    with open(spice_path, "r") as f:
-        lines = f.readlines()
-
-    subckt_line_index = next((i for i, line in enumerate(lines) if line.strip().lower().startswith(".subckt")), None)
-    if subckt_line_index is None:
-        raise ValueError(f"No .subckt line found in SPICE file: {spice_path}")
-
-    parts = lines[subckt_line_index].strip().split()
-    subckt_name = parts[1]
-    new_subckt_name = subckt_name
-    parts[1] = new_subckt_name
-    lines[subckt_line_index] = ' '.join(parts) + '\n'
-
-    definition_lines = []
-    recording = False
-    for line in lines:
-        if line.strip().lower().startswith(".subckt"):
-            recording = True
-        if recording:
-            definition_lines.append(line.rstrip())
-        if line.strip().lower() == ".ends":
-            break
-
-    return new_subckt_name, '\n'.join(definition_lines)
-
-def find_subckt_location(subckt_name, schematic_file):
-    text_content = load_text_file(schematic_file)
-    return text_content.find(subckt_name + '.sym')
-
-def find_first_curly_brackets_span(text, start_pos):
-    open_pos = text.find('{', start_pos)
-    if open_pos == -1:
-        return None, None
-
-    depth = 1
-    for i in range(open_pos + 1, len(text)):
-        if text[i] == '{':
-            depth += 1
-        elif text[i] == '}':
-            depth -= 1
-            if depth == 0:
-                return open_pos, i
-    return None, None
-
-def replace_curly_brackets_content(text, start_idx, end_idx, new_content, subckt_name):
-    content = text[start_idx+1:end_idx].strip('\n ')
-    lines = content.splitlines()
-
-    name_line_index = next((i for i, line in enumerate(lines) if line.strip().startswith("name=")), None)
-    schematic_line = "schematic=" + subckt_name
-    if name_line_index is None:
-        new_lines = ['spice_sym_def="', new_content.strip(), '"'] + lines
-    else:
-        new_lines = (
-            lines[:name_line_index+1] +
-            [schematic_line] +
-            ['spice_sym_def="', new_content.strip(), '"'] +
-            lines[name_line_index+1:]
-        )
-
-    return text[:start_idx+1] + '\n' + '\n'.join(new_lines) + '\n' + text[end_idx:]
-
-def process_pair(spice_path, schematic_path):
-    print(f"\nProcessing:\n  SPICE: {spice_path}\n  Schematic: {schematic_path}")
-    try:
-        subckt_name, definition = read_spice_definition(spice_path)
-        print(f"  Subcircuit name: {subckt_name}")
-    except Exception as e:
-        print(f"  Error reading spice file: {e}")
-        return
-
-    # If subckt_name ends with '_pex', strip it for schematic search
-    search_subckt_name = subckt_name
-    if subckt_name.endswith("_pex"):
-        search_subckt_name = subckt_name[:-4]
-
-    location = find_subckt_location(search_subckt_name, schematic_path)
-    if location == -1:
-        print(f"  '{search_subckt_name}.sym' not found in schematic file.")
-        return
-
-    schematic_content = load_text_file(schematic_path)
-    start_idx, end_idx = find_first_curly_brackets_span(schematic_content, location)
-    if start_idx is None:
-        print("  No matching curly brackets found after .sym device.")
-        return
-
-    new_schematic_content = replace_curly_brackets_content(
-        schematic_content, start_idx, end_idx, definition, subckt_name
-    )
-
-    # Save the file in the current working directory (where script is run)
-    base_name = os.path.basename(schematic_path)
-    name, ext = os.path.splitext(base_name)
-    new_filename = os.path.join(os.getcwd(), f"{name}_pex{ext}")
-
-    save_text_file(new_filename, new_schematic_content)
-    
-    print(f"  Replacement done and new schematic file saved as:\n    {new_filename}")
-
-if __name__ == "__main__":
-    if len(sys.argv) != 3:
-        print("Usage:\n  python3 script.py <schematic.sch> <spice_file.spice>")
-        sys.exit(1)
-
-    schematic = sys.argv[1]
-    spice_path = sys.argv[2]
-
-    print(f"Starting processing with schematic='{schematic}', spice='{spice_path}'")  # Debug print
-
-    process_pair(spice_path, schematic)

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/xschem_rc.py

@@ -1,37 +0,0 @@
-import sys
-def generate_xschemrc(custom_paths):
-    lines = [
-        "# xschemrc - Custom configuration file for xschem",
-        "# This file sources another xschemrc file from a known location",
-        "",
-        "# Source the base configuration from a known location",
-        "source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc",
-        "",
-        "# (Optional) Add any custom overrides or extensions below",
-        '# set xschem_library_path /home/user/my_libs',
-        '# set xschem_gui_font "Monospace 10"',
-        "",
-        "append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem"
-    ]
-
-    # Append each custom path with the prefix "../"
-    for path in custom_paths:
-        lines.append(f"append XSCHEM_LIBRARY_PATH :{path}")
-
-    return "\n".join(lines) + "\n"
-
-def main():
-    if len(sys.argv) < 2:
-        print("Usage: python3 make_xschemrc.py <path1> [<path2> ... <pathN>]")
-        sys.exit(1)
-
-    custom_paths = sys.argv[1:]
-    content = generate_xschemrc(custom_paths)
-
-    with open("xschemrc", "w") as f:
-        f.write(content)
-
-    print(f"xschemrc file generated with {len(custom_paths)} custom paths.")
-
-if __name__ == "__main__":
-    main()

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/run_kpex.sh

@@ -14,7 +14,7 @@ KPEX_MAGIC_EXE="$HOME/.local/bin/magic"
 # Example: /usr/local/bin/magic or ~/.local/bin/magic
 
 #Path to symbol
-SYM_DIR="../xschem_pre_layout/schematic/DIFF_COMPARATOR.sym"       # Asuming you have a symbol for the DUT
+SYM_DIR="./DIFF_COMPARATOR.sym"       # Asuming you have a symbol for the DUT
 
 LAYOUT_DIR="../layout/DIFF_COMPARATOR.gds"        # Path to the GDS file
 

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/xschem_pex_symbol/DIFF_COMPARATOR.sym

@@ -21,43 +21,43 @@ X9 gnd clk a_944_1911# gnd sg13_lv_nmos ad=0.76p pd=4.38u as=1.44p ps=4.72u w=4u
 X10 out- a_687_2445# vdd vdd sg13_lv_pmos ad=1.36p pd=8.68u as=0.76p ps=4.38u w=4u l=0.2u M=2
 X11 out+ a_944_1911# gnd gnd sg13_lv_nmos ad=0.68p pd=4.68u as=0.38p ps=2.38u w=2u l=0.2u M=2
 X12 a_1245_3300# clk a_1752_817# vdd sg13_lv_pmos ad=1.53p pd=9.68u as=0.855p ps=4.88u w=4.5u l=0.3u M=4
-C0 a_1752_817# a_1245_3300# 3.76533f
+C0 a_944_1911# V- 0.46901f
-C1 a_944_1911# a_1245_3300# 8.04522f
+C1 a_944_1911# vdd 1.10862f
-C2 out- out+ 0.0933f
+C2 a_687_2445# V- 0.78527f
-C3 clk a_1245_3300# 0.44782f
+C3 a_687_2445# vdd 1.31156f
-C4 w_805_2869# vdd 0.1537f
+C4 clk a_1245_3300# 0.44782f
-C5 V+ a_1245_3300# 0.76573f
+C5 out+ a_1245_3300# 0.36924f
-C6 V- a_1245_3300# 0.94179f
+C6 out- a_1245_3300# 0.36795f
-C7 a_1245_3300# vdd 2.55093f
+C7 V+ a_1245_3300# 0.76573f
-C8 a_944_1911# a_1752_817# 0.0558f
+C8 vdd a_1752_817# 7.11146f
-C9 a_1245_3300# a_687_2445# 11.3534f
+C9 clk a_944_1911# 0.24743f
-C10 a_1752_817# vbias 2.28993f
+C10 clk a_687_2445# 0.23833f
-C11 a_1752_817# clk 0.5025f
+C11 out+ a_944_1911# 0.80028f
-C12 a_944_1911# clk 0.24743f
+C12 out+ a_687_2445# 0.69286f
-C13 V+ a_944_1911# 1.08178f
+C13 a_944_1911# out- 0.61161f
-C14 V- a_944_1911# 0.46901f
+C14 a_944_1911# V+ 1.08178f
-C15 a_1245_3300# out+ 0.36924f
+C15 a_687_2445# out- 0.89453f
-C16 clk vbias 0.19878f
+C16 a_687_2445# V+ 0.13025f
-C17 a_1245_3300# out- 0.36795f
+C17 clk a_1752_817# 0.5025f
-C18 a_1752_817# vdd 7.11146f
+C18 vdd V- 4.06121f
-C19 a_1752_817# a_687_2445# 0.04531f
+C19 clk vdd 2.98842f
-C20 a_944_1911# vdd 1.10862f
+C20 out+ vdd 1.84773f
-C21 a_944_1911# a_687_2445# 2.24936f
+C21 a_1752_817# vbias 2.28993f
-C22 vbias vdd 2.83964f
+C22 V- V+ 1.61045f
-C23 clk vdd 2.98842f
+C23 vdd out- 1.84304f
-C24 V- V+ 1.61045f
+C24 vdd V+ 4.08205f
-C25 clk a_687_2445# 0.23833f
+C25 a_944_1911# a_1245_3300# 8.04522f
-C26 V+ vdd 4.08205f
+C26 a_687_2445# a_1245_3300# 11.3534f
-C27 V- vdd 4.06121f
+C27 a_1752_817# a_1245_3300# 3.76533f
-C28 V+ a_687_2445# 0.13025f
+C28 out+ out- 0.0933f
-C29 V- a_687_2445# 0.78527f
+C29 a_687_2445# a_944_1911# 2.24936f
-C30 a_944_1911# out+ 0.80028f
+C30 vdd vbias 2.83964f
-C31 a_944_1911# out- 0.61161f
+C31 a_944_1911# a_1752_817# 0.0558f
-C32 a_687_2445# vdd 1.31156f
+C32 a_687_2445# a_1752_817# 0.04531f
-C33 vdd out+ 1.84773f
+C33 clk vbias 0.19878f
-C34 a_687_2445# out+ 0.69286f
+C34 V- a_1245_3300# 0.94179f
-C35 vdd out- 1.84304f
+C35 vdd a_1245_3300# 2.55093f
-C36 a_687_2445# out- 0.89453f
+C36 vdd w_805_2869# 0.1537f
 R0 V+.n6 V+.n0 17.1875
 R1 V+.n6 V+.n5 16.5321
 R2 V+.n2 V+.n1 15.8046

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/schematic/DIFF_COMPARATOR.sym

@@ -0,0 +1,39 @@
+v {xschem version=3.4.5 file_version=1.2
+}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -100 130 0 {}
+L 4 -130 100 130 0 {}
+L 4 -130 -100 -130 100 {}
+L 4 -150 0 -130 0 {}
+L 4 -150 -60 -130 -60 {}
+L 4 -150 60 -130 60 {}
+L 4 110 10 130 10 {}
+L 4 110 -10 130 -10 {}
+L 4 -20 60 -20 80 {}
+L 7 -70 -100 -70 -80 {}
+L 7 -70 80 -70 100 {}
+B 5 -72.5 -102.5 -67.5 -97.5 {name=vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=vbias dir=in}
+B 5 -152.5 -62.5 -147.5 -57.5 {name=v+ dir=in}
+B 5 -152.5 57.5 -147.5 62.5 {name=v- dir=in}
+B 5 127.5 7.5 132.5 12.5 {name=out- dir=out}
+B 5 127.5 -12.5 132.5 -7.5 {name=out+ dir=out}
+B 5 -22.5 77.5 -17.5 82.5 {name=clk dir=in}
+B 5 -72.5 97.5 -67.5 102.5 {name=gnd dir=inout}
+T {@symname} -89 -6 0 0 0.3 0.3 {}
+T {@name} 25 -52 0 0 0.2 0.2 {}
+T {vdd} -74 -75 3 1 0.2 0.2 {}
+T {vbias} -125 -4 0 0 0.2 0.2 {}
+T {v+} -125 -64 0 0 0.2 0.2 {}
+T {v-} -125 56 0 0 0.2 0.2 {}
+T {out-} 90 1 0 1 0.2 0.2 {}
+T {out+} 95 -14 0 1 0.2 0.2 {}
+T {clk} -24 55 3 0 0.2 0.2 {}
+T {gnd} -66 75 1 1 0.2 0.2 {}

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/comparator_tb.sch

@@ -6,7 +6,7 @@ S {}
 E {}
 B 2 20 -1225 820 -825 {flags=graph
 y1=0
-y2=1.3
+y2=1.2
 ypos1=0
 ypos2=2
 divy=5
@@ -78,8 +78,8 @@ x2=1e-06
 color=4
 node=vout}
 B 2 850 -805 1650 -405 {flags=graph
-y1=1.1
+y1=-0.027
-y2=1.2
+y2=1.3
 ypos1=0
 ypos2=2
 divy=5
@@ -282,4 +282,912 @@ write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get curr
 xschem netlist
 simulate
 "}
-C {DIFF_COMPARATOR.sym} 270 -220 0 0 {name=x1}
+C {DIFF_COMPARATOR.sym} 270 -220 0 0 {name=x1
+schematic=DIFF_COMPARATOR_pex
+spice_sym_def=
+"
+.subckt DIFF_COMPARATOR_pex vdd gnd V+ V- clk out- out+ vbias
+X0 a_687_2445# V- a_1245_3300# vdd sg13_lv_pmos ad=0.76p pd=4.38u as=1.36p ps=8.68u w=4u l=0.2u M=8
+X1 a_944_1911# V+ a_1245_3300# vdd sg13_lv_pmos ad=0.76p pd=4.38u as=1.36p ps=8.68u w=4u l=0.2u M=8
+X2 a_1752_817# vbias vdd vdd sg13_lv_pmos ad=1.53p pd=9.68u as=0.855p ps=4.88u w=4.5u l=0.3u M=4
+X3 gnd gnd gnd gnd sg13_lv_nmos ad=1.36p pd=8.68u as=50.9002p ps=0.15373m w=4u l=0.2u M=4
+X4 vdd a_944_1911# out+ vdd sg13_lv_pmos ad=0.76p pd=4.38u as=1.36p ps=8.68u w=4u l=0.2u M=2
+X5 a_944_1911# a_687_2445# gnd gnd sg13_lv_nmos ad=1.44p pd=4.72u as=0.76p ps=4.38u w=4u l=0.2u
+X6 a_687_2445# clk gnd gnd sg13_lv_nmos ad=1.44p pd=4.72u as=0.76p ps=4.38u w=4u l=0.2u
+X7 gnd a_944_1911# a_687_2445# gnd sg13_lv_nmos ad=0.76p pd=4.38u as=1.44p ps=4.72u w=4u l=0.2u
+X8 out- a_687_2445# gnd gnd sg13_lv_nmos ad=0.68p pd=4.68u as=0.38p ps=2.38u w=2u l=0.2u M=2
+X9 gnd clk a_944_1911# gnd sg13_lv_nmos ad=0.76p pd=4.38u as=1.44p ps=4.72u w=4u l=0.2u
+X10 out- a_687_2445# vdd vdd sg13_lv_pmos ad=1.36p pd=8.68u as=0.76p ps=4.38u w=4u l=0.2u M=2
+X11 out+ a_944_1911# gnd gnd sg13_lv_nmos ad=0.68p pd=4.68u as=0.38p ps=2.38u w=2u l=0.2u M=2
+X12 a_1245_3300# clk a_1752_817# vdd sg13_lv_pmos ad=1.53p pd=9.68u as=0.855p ps=4.88u w=4.5u l=0.3u M=4
+C0 a_944_1911# V- 0.46901f
+C1 a_944_1911# vdd 1.10862f
+C2 a_687_2445# V- 0.78527f
+C3 a_687_2445# vdd 1.31156f
+C4 clk a_1245_3300# 0.44782f
+C5 out+ a_1245_3300# 0.36924f
+C6 out- a_1245_3300# 0.36795f
+C7 V+ a_1245_3300# 0.76573f
+C8 vdd a_1752_817# 7.11146f
+C9 clk a_944_1911# 0.24743f
+C10 clk a_687_2445# 0.23833f
+C11 out+ a_944_1911# 0.80028f
+C12 out+ a_687_2445# 0.69286f
+C13 a_944_1911# out- 0.61161f
+C14 a_944_1911# V+ 1.08178f
+C15 a_687_2445# out- 0.89453f
+C16 a_687_2445# V+ 0.13025f
+C17 clk a_1752_817# 0.5025f
+C18 vdd V- 4.06121f
+C19 clk vdd 2.98842f
+C20 out+ vdd 1.84773f
+C21 a_1752_817# vbias 2.28993f
+C22 V- V+ 1.61045f
+C23 vdd out- 1.84304f
+C24 vdd V+ 4.08205f
+C25 a_944_1911# a_1245_3300# 8.04522f
+C26 a_687_2445# a_1245_3300# 11.3534f
+C27 a_1752_817# a_1245_3300# 3.76533f
+C28 out+ out- 0.0933f
+C29 a_687_2445# a_944_1911# 2.24936f
+C30 vdd vbias 2.83964f
+C31 a_944_1911# a_1752_817# 0.0558f
+C32 a_687_2445# a_1752_817# 0.04531f
+C33 clk vbias 0.19878f
+C34 V- a_1245_3300# 0.94179f
+C35 vdd a_1245_3300# 2.55093f
+C36 vdd w_805_2869# 0.1537f
+R0 V+.n6 V+.n0 17.1875
+R1 V+.n6 V+.n5 16.5321
+R2 V+.n2 V+.n1 15.8046
+R3 V+.n4 V+.n3 9.60223
+R4 V+.n4 V+.n1 8.28871
+R5 V+.n3 V+.n0 8.28871
+R6 V+.n5 V+.n4 7.51146
+R7 V+.n3 V+.n2 7.51146
+R8 V+ V+.n6 1.77098
+R9 V-.n6 V-.n0 17.1792
+R10 V-.n3 V-.n0 17.1129
+R11 V-.n4 V-.n1 17.1083
+R12 V-.n6 V-.n5 16.5321
+R13 V-.n2 V-.n1 15.8156
+R14 V-.n5 V-.n4 7.51146
+R15 V-.n3 V-.n2 7.51146
+R16 V- V-.n6 1.57783
+R17 V-.n4 V-.n3 0.792909
+R18 vbias vbias.n0 6.1153
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+R670 gnd.n101 gnd.n19 8.501
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+R675 gnd.n28 gnd.n24 8.49127
+R676 gnd.n28 gnd.n27 8.49127
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+R715 gnd.n130 gnd.n129 1.10932
+R716 gnd.n2 gnd.n1 1.1005
+R717 gnd.n39 gnd.n38 1.1005
+R718 gnd.n47 gnd.n46 1.1005
+R719 gnd.n49 gnd.n48 1.1005
+R720 gnd.n81 gnd.n52 0.846373
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+R722 gnd.n40 gnd.n17 0.552785
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+R735 gnd.n40 gnd.n18 0.395917
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+R742 gnd.n44 gnd.n22 0.306266
+R743 gnd.n128 gnd.n3 0.305337
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+R745 gnd.n80 gnd.n79 0.294146
+R746 gnd.n106 gnd.n105 0.288586
+R747 gnd.n107 gnd.n106 0.288586
+R748 gnd.n105 gnd.n104 0.249692
+R749 gnd.n33 gnd.n32 0.247403
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+R753 gnd.n79 gnd.n78 0.227375
+R754 gnd.n78 gnd.n63 0.227375
+R755 gnd.n32 gnd.n30 0.227375
+R756 gnd.n117 gnd.n116 0.227375
+R757 gnd.n116 gnd.n114 0.227375
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+R759 gnd.n36 gnd.n23 0.0828779
+R760 gnd.n16 gnd.n5 0.0744717
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+R762 gnd.n13 gnd.n8 0.0405896
+R763 gnd.n15 gnd.n6 0.0405896
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+R827 gnd.n65 gnd.n53 0.00333088
+R828 gnd.n109 gnd.n94 0.00333088
+R829 gnd.n131 gnd 0.0014625
+R830 gnd.n126 gnd.n19 0.001
+R831 gnd.n103 gnd.n102 0.001
+R832 gnd.n99 gnd.n98 0.001
+R833 gnd.n100 gnd.n97 0.001
+R834 gnd.n96 gnd.n95 0.001
+R835 gnd.n103 gnd.n19 0.001
+R836 gnd.n126 gnd.n95 0.001
+R837 gnd.n100 gnd.n96 0.001
+R838 gnd.n99 gnd.n97 0.001
+R839 gnd.n102 gnd.n98 0.001
+C37 vbias gnd 2.83431f
+C38 clk gnd 7.89606f
+C39 out+ gnd 2.36194f
+C40 out- gnd 2.35875f
+C41 V+ gnd 3.9126f
+C42 V- gnd 3.93119f
+C43 vdd gnd 17.9739f
+C44 a_1752_817# gnd 0.44266f $ **FLOATING
+C45 a_944_1911# gnd 4.28617f $ **FLOATING
+C46 a_687_2445# gnd 4.01269f $ **FLOATING
+C47 a_1245_3300# gnd 1.43203f $ **FLOATING
+.ends
+"
+}

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/offset_MC_analysis.sch

@@ -136,7 +136,7 @@ value="
 .endc
 
 "}
-C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/xschem_pex_symbol/DIFF_COMPARATOR.sym} 270 -220 0 0 {name=x1
+C {DIFF_COMPARATOR.sym} 270 -220 0 0 {name=x1
 schematic=DIFF_COMPARATOR_pex
 spice_sym_def=
 "
@@ -154,43 +154,43 @@ X9 gnd clk a_944_1911# gnd sg13_lv_nmos ad=0.76p pd=4.38u as=1.44p ps=4.72u w=4u
 X10 out- a_687_2445# vdd vdd sg13_lv_pmos ad=1.36p pd=8.68u as=0.76p ps=4.38u w=4u l=0.2u M=2
 X11 out+ a_944_1911# gnd gnd sg13_lv_nmos ad=0.68p pd=4.68u as=0.38p ps=2.38u w=2u l=0.2u M=2
 X12 a_1245_3300# clk a_1752_817# vdd sg13_lv_pmos ad=1.53p pd=9.68u as=0.855p ps=4.88u w=4.5u l=0.3u M=4
-C0 a_1752_817# a_1245_3300# 3.76533f
+C0 a_944_1911# V- 0.46901f
-C1 a_944_1911# a_1245_3300# 8.04522f
+C1 a_944_1911# vdd 1.10862f
-C2 out- out+ 0.0933f
+C2 a_687_2445# V- 0.78527f
-C3 clk a_1245_3300# 0.44782f
+C3 a_687_2445# vdd 1.31156f
-C4 w_805_2869# vdd 0.1537f
+C4 clk a_1245_3300# 0.44782f
-C5 V+ a_1245_3300# 0.76573f
+C5 out+ a_1245_3300# 0.36924f
-C6 V- a_1245_3300# 0.94179f
+C6 out- a_1245_3300# 0.36795f
-C7 a_1245_3300# vdd 2.55093f
+C7 V+ a_1245_3300# 0.76573f
-C8 a_944_1911# a_1752_817# 0.0558f
+C8 vdd a_1752_817# 7.11146f
-C9 a_1245_3300# a_687_2445# 11.3534f
+C9 clk a_944_1911# 0.24743f
-C10 a_1752_817# vbias 2.28993f
+C10 clk a_687_2445# 0.23833f
-C11 a_1752_817# clk 0.5025f
+C11 out+ a_944_1911# 0.80028f
-C12 a_944_1911# clk 0.24743f
+C12 out+ a_687_2445# 0.69286f
-C13 V+ a_944_1911# 1.08178f
+C13 a_944_1911# out- 0.61161f
-C14 V- a_944_1911# 0.46901f
+C14 a_944_1911# V+ 1.08178f
-C15 a_1245_3300# out+ 0.36924f
+C15 a_687_2445# out- 0.89453f
-C16 clk vbias 0.19878f
+C16 a_687_2445# V+ 0.13025f
-C17 a_1245_3300# out- 0.36795f
+C17 clk a_1752_817# 0.5025f
-C18 a_1752_817# vdd 7.11146f
+C18 vdd V- 4.06121f
-C19 a_1752_817# a_687_2445# 0.04531f
+C19 clk vdd 2.98842f
-C20 a_944_1911# vdd 1.10862f
+C20 out+ vdd 1.84773f
-C21 a_944_1911# a_687_2445# 2.24936f
+C21 a_1752_817# vbias 2.28993f
-C22 vbias vdd 2.83964f
+C22 V- V+ 1.61045f
-C23 clk vdd 2.98842f
+C23 vdd out- 1.84304f
-C24 V- V+ 1.61045f
+C24 vdd V+ 4.08205f
-C25 clk a_687_2445# 0.23833f
+C25 a_944_1911# a_1245_3300# 8.04522f
-C26 V+ vdd 4.08205f
+C26 a_687_2445# a_1245_3300# 11.3534f
-C27 V- vdd 4.06121f
+C27 a_1752_817# a_1245_3300# 3.76533f
-C28 V+ a_687_2445# 0.13025f
+C28 out+ out- 0.0933f
-C29 V- a_687_2445# 0.78527f
+C29 a_687_2445# a_944_1911# 2.24936f
-C30 a_944_1911# out+ 0.80028f
+C30 vdd vbias 2.83964f
-C31 a_944_1911# out- 0.61161f
+C31 a_944_1911# a_1752_817# 0.0558f
-C32 a_687_2445# vdd 1.31156f
+C32 a_687_2445# a_1752_817# 0.04531f
-C33 vdd out+ 1.84773f
+C33 clk vbias 0.19878f
-C34 a_687_2445# out+ 0.69286f
+C34 V- a_1245_3300# 0.94179f
-C35 vdd out- 1.84304f
+C35 vdd a_1245_3300# 2.55093f
-C36 a_687_2445# out- 0.89453f
+C36 vdd w_805_2869# 0.1537f
 R0 V+.n6 V+.n0 17.1875
 R1 V+.n6 V+.n5 16.5321
 R2 V+.n2 V+.n1 15.8046

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/simulations/comparator_tb.save

@@ -1,132 +1,2 @@
 * Place this .save file with a .include line in your testbench
 
-.save @n.x1.xm2.nsg13_lv_pmos[ids]
-.save @n.x1.xm2.nsg13_lv_pmos[gm]
-.save @n.x1.xm2.nsg13_lv_pmos[gds]
-.save @n.x1.xm2.nsg13_lv_pmos[vth]
-.save @n.x1.xm2.nsg13_lv_pmos[vgs]
-.save @n.x1.xm2.nsg13_lv_pmos[vdss]
-.save @n.x1.xm2.nsg13_lv_pmos[vds]
-.save @n.x1.xm2.nsg13_lv_pmos[cgg]
-.save @n.x1.xm2.nsg13_lv_pmos[cgsol]
-.save @n.x1.xm2.nsg13_lv_pmos[cgdol]
-.save @n.x1.xm1.nsg13_lv_pmos[ids]
-.save @n.x1.xm1.nsg13_lv_pmos[gm]
-.save @n.x1.xm1.nsg13_lv_pmos[gds]
-.save @n.x1.xm1.nsg13_lv_pmos[vth]
-.save @n.x1.xm1.nsg13_lv_pmos[vgs]
-.save @n.x1.xm1.nsg13_lv_pmos[vdss]
-.save @n.x1.xm1.nsg13_lv_pmos[vds]
-.save @n.x1.xm1.nsg13_lv_pmos[cgg]
-.save @n.x1.xm1.nsg13_lv_pmos[cgsol]
-.save @n.x1.xm1.nsg13_lv_pmos[cgdol]
-.save @n.x1.xm4.nsg13_lv_pmos[ids]
-.save @n.x1.xm4.nsg13_lv_pmos[gm]
-.save @n.x1.xm4.nsg13_lv_pmos[gds]
-.save @n.x1.xm4.nsg13_lv_pmos[vth]
-.save @n.x1.xm4.nsg13_lv_pmos[vgs]
-.save @n.x1.xm4.nsg13_lv_pmos[vdss]
-.save @n.x1.xm4.nsg13_lv_pmos[vds]
-.save @n.x1.xm4.nsg13_lv_pmos[cgg]
-.save @n.x1.xm4.nsg13_lv_pmos[cgsol]
-.save @n.x1.xm4.nsg13_lv_pmos[cgdol]
-.save @n.x1.xm5.nsg13_lv_pmos[ids]
-.save @n.x1.xm5.nsg13_lv_pmos[gm]
-.save @n.x1.xm5.nsg13_lv_pmos[gds]
-.save @n.x1.xm5.nsg13_lv_pmos[vth]
-.save @n.x1.xm5.nsg13_lv_pmos[vgs]
-.save @n.x1.xm5.nsg13_lv_pmos[vdss]
-.save @n.x1.xm5.nsg13_lv_pmos[vds]
-.save @n.x1.xm5.nsg13_lv_pmos[cgg]
-.save @n.x1.xm5.nsg13_lv_pmos[cgsol]
-.save @n.x1.xm5.nsg13_lv_pmos[cgdol]
-.save @n.x1.xm11.nsg13_lv_nmos[ids]
-.save @n.x1.xm11.nsg13_lv_nmos[gm]
-.save @n.x1.xm11.nsg13_lv_nmos[gds]
-.save @n.x1.xm11.nsg13_lv_nmos[vth]
-.save @n.x1.xm11.nsg13_lv_nmos[vgs]
-.save @n.x1.xm11.nsg13_lv_nmos[vdss]
-.save @n.x1.xm11.nsg13_lv_nmos[vds]
-.save @n.x1.xm11.nsg13_lv_nmos[cgg]
-.save @n.x1.xm11.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm11.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm12.nsg13_lv_nmos[ids]
-.save @n.x1.xm12.nsg13_lv_nmos[gm]
-.save @n.x1.xm12.nsg13_lv_nmos[gds]
-.save @n.x1.xm12.nsg13_lv_nmos[vth]
-.save @n.x1.xm12.nsg13_lv_nmos[vgs]
-.save @n.x1.xm12.nsg13_lv_nmos[vdss]
-.save @n.x1.xm12.nsg13_lv_nmos[vds]
-.save @n.x1.xm12.nsg13_lv_nmos[cgg]
-.save @n.x1.xm12.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm12.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm6.nsg13_lv_nmos[ids]
-.save @n.x1.xm6.nsg13_lv_nmos[gm]
-.save @n.x1.xm6.nsg13_lv_nmos[gds]
-.save @n.x1.xm6.nsg13_lv_nmos[vth]
-.save @n.x1.xm6.nsg13_lv_nmos[vgs]
-.save @n.x1.xm6.nsg13_lv_nmos[vdss]
-.save @n.x1.xm6.nsg13_lv_nmos[vds]
-.save @n.x1.xm6.nsg13_lv_nmos[cgg]
-.save @n.x1.xm6.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm6.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm10.nsg13_lv_nmos[ids]
-.save @n.x1.xm10.nsg13_lv_nmos[gm]
-.save @n.x1.xm10.nsg13_lv_nmos[gds]
-.save @n.x1.xm10.nsg13_lv_nmos[vth]
-.save @n.x1.xm10.nsg13_lv_nmos[vgs]
-.save @n.x1.xm10.nsg13_lv_nmos[vdss]
-.save @n.x1.xm10.nsg13_lv_nmos[vds]
-.save @n.x1.xm10.nsg13_lv_nmos[cgg]
-.save @n.x1.xm10.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm10.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm7.nsg13_lv_nmos[ids]
-.save @n.x1.xm7.nsg13_lv_nmos[gm]
-.save @n.x1.xm7.nsg13_lv_nmos[gds]
-.save @n.x1.xm7.nsg13_lv_nmos[vth]
-.save @n.x1.xm7.nsg13_lv_nmos[vgs]
-.save @n.x1.xm7.nsg13_lv_nmos[vdss]
-.save @n.x1.xm7.nsg13_lv_nmos[vds]
-.save @n.x1.xm7.nsg13_lv_nmos[cgg]
-.save @n.x1.xm7.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm7.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm8.nsg13_lv_nmos[ids]
-.save @n.x1.xm8.nsg13_lv_nmos[gm]
-.save @n.x1.xm8.nsg13_lv_nmos[gds]
-.save @n.x1.xm8.nsg13_lv_nmos[vth]
-.save @n.x1.xm8.nsg13_lv_nmos[vgs]
-.save @n.x1.xm8.nsg13_lv_nmos[vdss]
-.save @n.x1.xm8.nsg13_lv_nmos[vds]
-.save @n.x1.xm8.nsg13_lv_nmos[cgg]
-.save @n.x1.xm8.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm8.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm3.nsg13_lv_nmos[ids]
-.save @n.x1.xm3.nsg13_lv_nmos[gm]
-.save @n.x1.xm3.nsg13_lv_nmos[gds]
-.save @n.x1.xm3.nsg13_lv_nmos[vth]
-.save @n.x1.xm3.nsg13_lv_nmos[vgs]
-.save @n.x1.xm3.nsg13_lv_nmos[vdss]
-.save @n.x1.xm3.nsg13_lv_nmos[vds]
-.save @n.x1.xm3.nsg13_lv_nmos[cgg]
-.save @n.x1.xm3.nsg13_lv_nmos[cgsol]
-.save @n.x1.xm3.nsg13_lv_nmos[cgdol]
-.save @n.x1.xm13.nsg13_lv_pmos[ids]
-.save @n.x1.xm13.nsg13_lv_pmos[gm]
-.save @n.x1.xm13.nsg13_lv_pmos[gds]
-.save @n.x1.xm13.nsg13_lv_pmos[vth]
-.save @n.x1.xm13.nsg13_lv_pmos[vgs]
-.save @n.x1.xm13.nsg13_lv_pmos[vdss]
-.save @n.x1.xm13.nsg13_lv_pmos[vds]
-.save @n.x1.xm13.nsg13_lv_pmos[cgg]
-.save @n.x1.xm13.nsg13_lv_pmos[cgsol]
-.save @n.x1.xm13.nsg13_lv_pmos[cgdol]
-.save @n.x1.xm9.nsg13_lv_pmos[ids]
-.save @n.x1.xm9.nsg13_lv_pmos[gm]
-.save @n.x1.xm9.nsg13_lv_pmos[gds]
-.save @n.x1.xm9.nsg13_lv_pmos[vth]
-.save @n.x1.xm9.nsg13_lv_pmos[vgs]
-.save @n.x1.xm9.nsg13_lv_pmos[vdss]
-.save @n.x1.xm9.nsg13_lv_pmos[vds]
-.save @n.x1.xm9.nsg13_lv_pmos[cgg]
-.save @n.x1.xm9.nsg13_lv_pmos[cgsol]
-.save @n.x1.xm9.nsg13_lv_pmos[cgdol]

modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/xschem_post_layout/testbench/xschemrc

@@ -14,6 +14,5 @@ source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
 
 
 #### Add custom libraries (directories with .lib files)
-append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
+append XSCHEM_LIBRARY_PATH :../../pex/xschem_pex_symbol/
-append XSCHEM_LIBRARY_PATH :../schematic/