luke
/
IHP-AnalogAcademy
mirror of https://github.com/IHP-GmbH/IHP-AnalogAcademy.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

update OTA layout content

This commit is contained in:
PhillipRambo 2025-01-08 08:25:33 +01:00
parent 2031391a13
commit e5e1c41028
3 changed files with 57 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid.gds
View File

Binary file not shown.

2
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid_extracted.cir
View File

@ -1,4 +1,4 @@
* Extracted by KLayout with SG13G2 LVS runset on : 07/01/2025 08:25
* Extracted by KLayout with SG13G2 LVS runset on : 07/01/2025 13:14
.SUBCKT input_common_centroid v\x2d vdd v+ dn4 dn3
M$1 vdd vdd \$7 \$3 sg13_lv_pmos L=3.7u W=14.56u AS=4.9504p AD=4.9504p

112
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch
View File

@ -5,63 +5,63 @@ K {}
V {}
S {}
E {}
N 450 -495 450 -395 {
N 610 -485 610 -385 {
lab=dn3}
N 450 -575 450 -555 {
N 610 -565 610 -545 {
lab=dn2}
N 660 -575 660 -555 {
N 820 -565 820 -545 {
lab=dn2}
N 560 -575 660 -575 {
N 720 -565 820 -565 {
lab=dn2}
N 380 -525 410 -525 {
N 540 -515 570 -515 {
lab=v-}
N 700 -525 730 -525 {
N 860 -515 890 -515 {
lab=v+}
N 560 -595 560 -575 {
N 720 -585 720 -565 {
lab=dn2}
N 450 -575 560 -575 {
N 610 -565 720 -565 {
lab=dn2}
N 660 -495 660 -400 {
N 820 -485 820 -390 {
lab=dn4}
N 230 -315 230 -285 {
N 250 -335 250 -305 {
lab=vdd}
N 270 -255 270 -235 {
N 290 -275 290 -255 {
lab=dn4}
N 35 -315 35 -285 {
N 55 -335 55 -305 {
lab=vdd}
N 75 -255 75 -235 {
N 95 -275 95 -255 {
lab=dn3}
N 230 -315 270 -315 {
N 250 -335 290 -335 {
lab=vdd}
N 35 -315 75 -315 {
N 55 -335 95 -335 {
lab=vdd}
N 230 -425 230 -395 {
N 250 -445 250 -415 {
lab=vdd}
N 270 -365 270 -345 {
N 290 -385 290 -365 {
lab=dn2}
N 35 -425 35 -395 {
N 55 -445 55 -415 {
lab=vdd}
N 75 -365 75 -345 {
N 95 -385 95 -365 {
lab=dn2}
N 230 -425 270 -425 {
N 250 -445 290 -445 {
lab=vdd}
N 35 -425 75 -425 {
N 55 -445 95 -445 {
lab=vdd}
N 560 -245 560 -205 {
N 650 -215 650 -175 {
lab=vdd}
N 75 -285 180 -285 {
N 95 -305 200 -305 {
lab=bulk}
N 75 -395 180 -395 {
N 95 -415 200 -415 {
lab=bulk}
N 450 -525 660 -525 {
N 610 -515 820 -515 {
lab=bulk}
N 270 -395 375 -395 {
N 290 -415 395 -415 {
lab=bulk}
N 270 -285 375 -285 {
N 290 -305 395 -305 {
lab=bulk}
N 560 -325 560 -300 {
N 650 -295 650 -270 {
lab=bulk}
C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1
C {sg13g2_pr/sg13_lv_pmos.sym} 590 -515 0 0 {name=M1
l=3.7u
w=3.64u
ng=1
@ -69,7 +69,7 @@ m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 680 -525 0 1 {name=M2
C {sg13g2_pr/sg13_lv_pmos.sym} 840 -515 0 1 {name=M2
l=3.7u
w=3.64u
ng=1
@ -77,10 +77,10 @@ m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-}
C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+}
C {iopin.sym} 675 -205 2 1 {name=p1 lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 250 -285 0 0 {name=M8
C {iopin.sym} 540 -515 0 1 {name=p10 lab=v-}
C {iopin.sym} 890 -515 0 0 {name=p11 lab=v+}
C {iopin.sym} 735 -285 2 1 {name=p1 lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 270 -305 0 0 {name=M8
l=3.7u
w=3.64u
ng=1
@ -88,8 +88,8 @@ m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 230 -315 0 0 {name=p15 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 55 -285 0 0 {name=M10
C {lab_pin.sym} 250 -335 0 0 {name=p15 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 75 -305 0 0 {name=M10
l=3.7u
w=3.64u
ng=1
@ -97,11 +97,11 @@ m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 35 -315 0 0 {name=p17 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 560 -585 0 1 {name=p40 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 75 -235 0 0 {name=p43 sig_type=std_logic lab=dn3}
C {lab_pin.sym} 270 -235 0 0 {name=p18 sig_type=std_logic lab=dn4}
C {sg13g2_pr/sg13_lv_pmos.sym} 250 -395 0 0 {name=M15
C {lab_pin.sym} 55 -335 0 0 {name=p17 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 720 -575 0 1 {name=p40 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 95 -255 0 0 {name=p43 sig_type=std_logic lab=dn3}
C {lab_pin.sym} 290 -255 0 0 {name=p18 sig_type=std_logic lab=dn4}
C {sg13g2_pr/sg13_lv_pmos.sym} 270 -415 0 0 {name=M15
l=3.7u
w=3.64u
ng=1
@ -109,8 +109,8 @@ m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 230 -425 0 0 {name=p49 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 55 -395 0 0 {name=M16
C {lab_pin.sym} 250 -445 0 0 {name=p49 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 75 -415 0 0 {name=M16
l=3.7u
w=3.64u
ng=1
@ -118,21 +118,21 @@ m=2
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 35 -425 0 0 {name=p50 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 75 -345 0 0 {name=p53 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 270 -345 0 0 {name=p54 sig_type=std_logic lab=dn2}
C {sg13g2_pr/ntap1.sym} 560 -270 0 0 {name=R1
C {lab_pin.sym} 55 -445 0 0 {name=p50 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 95 -365 0 0 {name=p53 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 290 -365 0 0 {name=p54 sig_type=std_logic lab=dn2}
C {sg13g2_pr/ntap1.sym} 650 -240 0 0 {name=R1
model=ntap1
spiceprefix=X
w=13e-6
l=34e-6
}
C {iopin.sym} 450 -395 2 1 {name=p3 lab=dn3}
C {iopin.sym} 660 -405 2 1 {name=p4 lab=dn4}
C {lab_pin.sym} 560 -205 0 0 {name=p13 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 375 -395 0 1 {name=p2 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 180 -395 0 1 {name=p5 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 180 -285 0 1 {name=p6 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 375 -285 0 1 {name=p7 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 560 -325 0 1 {name=p8 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 560 -525 1 1 {name=p9 sig_type=std_logic lab=bulk}
C {iopin.sym} 610 -385 2 1 {name=p3 lab=dn3}
C {iopin.sym} 820 -395 2 1 {name=p4 lab=dn4}
C {lab_pin.sym} 650 -175 0 0 {name=p13 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 395 -415 0 1 {name=p2 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 200 -415 0 1 {name=p5 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 200 -305 0 1 {name=p6 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 395 -305 0 1 {name=p7 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 650 -295 0 1 {name=p8 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 720 -515 1 1 {name=p9 sig_type=std_logic lab=bulk}