remove .osdi file

.gitignore

@@ -3,3 +3,4 @@
 **/.ipynb_checkpoints/
 *.raw
 *.spice
+*.osdi

modules/module_1_bandgap_reference/part_1_OTA/schematic/ota_testbench.sch

@@ -201,6 +201,22 @@ N 95 200 200 200 {
 lab=#net4}
 N 95 260 95 280 {
 lab=GND}
+N 1300 330 1570 330 {
+lab=vout3}
+N 1180 330 1245 330 {
+lab=#net5}
+N 1180 390 1180 400 {
+lab=GND}
+N 1410 120 1570 120 {
+lab=vout3}
+N 1570 120 1570 330 {
+lab=vout3}
+N 1180 160 1210 160 {
+lab=#net5}
+N 1180 160 1180 330 {
+lab=#net5}
+N 1110 80 1210 80 {
+lab=vp}
 C {two_stage_OTA.sym} 360 -410 0 0 {name=x1}
 C {vsource.sym} 775 -205 0 0 {name=V1 value="DC 0.6 AC 1 0"
 }
@@ -298,3 +314,17 @@ C {lab_pin.sym} 335 65 0 0 {name=p8 sig_type=std_logic lab=VDDac}
 C {vsource.sym} 95 230 0 0 {name=V4 value="DC 0.6"
 }
 C {gnd.sym} 95 280 0 0 {name=l12 lab=GND}
+C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym} 1310 120 0 0 {name=U1 model=diff_amp_cell spiceprefix=X}
+C {ind.sym} 1275 330 1 0 {name=L16
+m=1
+value=4G
+footprint=1206
+device=inductor}
+C {capa.sym} 1180 360 0 0 {name=C3
+m=1
+value=4G
+footprint=1206
+device="ceramic capacitor"}
+C {gnd.sym} 1180 400 0 0 {name=l17 lab=GND}
+C {iopin.sym} 1570 120 0 0 {name=p9 lab=vout3}
+C {lab_pin.sym} 1110 80 0 0 {name=p14 sig_type=std_logic lab=vp}

modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/ota_testbench.spice

@@ -1,8 +1,9 @@
 ** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/ota_testbench.sch
-**.subckt ota_testbench vout vout1 vout2
+**.subckt ota_testbench vout vout1 vout2 vout3
 *.iopin vout
 *.iopin vout1
 *.iopin vout2
+*.iopin vout3
 x1 vdd net1 vp vm vout GND two_stage_OTA
 V1 vp GND DC 0.6 AC 1 0
 VDD vdd GND DC 1.2
@@ -19,6 +20,9 @@ L13 vout2 vm 4G m=1
 C2 vm GND 4G m=1
 V2 VDDac GND DC 1.2 AC 1 0
 V4 net4 GND DC 0.6
+XU1 vout3 vp net5 diff_amp_cell
+L16 vout3 net5 4G m=1
+C3 net5 GND 4G m=1
 **** begin user architecture code
 
 .lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ
@@ -59,8 +63,8 @@ write output_file.raw
 *.iopin vout
 XM4 net3 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
 XM3 net1 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
-XM1 net1 v- net2 vdd sg13_lv_pmos w=7.41u l=3.64u ng=1 m=1
-XM2 net3 v+ net2 vdd sg13_lv_pmos w=7.41u l=3.64u ng=1 m=1
+XM1 net1 v- net2 vdd sg13_lv_pmos w=3.705u l=3.64u ng=1 m=1
+XM2 net3 v+ net2 vdd sg13_lv_pmos w=3.705u l=3.64u ng=1 m=1
 XM5 net2 iout vdd vdd sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1
 XM7 vout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
 XM6 vout net3 vss vss sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1
@@ -69,4 +73,29 @@ XC2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1
 .ends
 
 .GLOBAL GND
+**** begin user architecture code
+
+
+.subckt diff_amp_cell OUT IN1 IN2
+
+N1 out in1 in2 diff_amp_model
+
+.ends diff_amp_cell
+
+
+
+.model diff_amp_model diff_amp
+
+
+
+.control
+
+* following line specifies the location for the .osdi file so ngspice can use it.
+
+pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.osdi
+
+.endc
+
+
+**** end user architecture code
 .end

modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch

@@ -107,7 +107,7 @@ spiceprefix=X
 }
 C {sg13g2_pr/sg13_lv_pmos.sym} 420 -370 0 0 {name=M1
 l=3.64u
-w=7.41u
+w=3.705u
 ng=1
 m=1
 model=sg13_lv_pmos
@@ -115,7 +115,7 @@ spiceprefix=X
 }
 C {sg13g2_pr/sg13_lv_pmos.sym} 670 -370 0 1 {name=M2
 l=3.64u
-w=7.41u
+w=3.705u
 ng=1
 m=1
 model=sg13_lv_pmos

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch

@@ -178,7 +178,7 @@ value="
 .lib $::SG13G2_MODELS/cornerRES.lib res_typ
 .lib cornerMOSlv.lib mos_tt
 "}
-C {sg13g2_pr/sg13_lv_nmos.sym} -700 -765 2 0 {name=M6
+C {sg13g2_pr/sg13_lv_nmos.sym} -700 -765 2 0 {name=M8
 l=10u
 w=150n
 ng=1
@@ -186,7 +186,7 @@ m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
-C {sg13g2_pr/sg13_lv_pmos.sym} -700 -930 0 1 {name=M7
+C {sg13g2_pr/sg13_lv_pmos.sym} -700 -930 0 1 {name=M6
 l=1u
 w=1u
 ng=1
@@ -194,7 +194,7 @@ m=1
 model=sg13_lv_pmos
 spiceprefix=X
 }
-C {sg13g2_pr/sg13_lv_pmos.sym} -595 -930 0 0 {name=M8
+C {sg13g2_pr/sg13_lv_pmos.sym} -595 -930 0 0 {name=M7
 l=1u
 w=1u
 ng=1
@@ -229,7 +229,7 @@ C {lab_pin.sym} -780 -930 0 0 {name=p17 sig_type=std_logic lab=vdd}
 C {vsource.sym} 1085 -590 0 0 {name=V1 value=1.2 savecurrent=false}
 C {lab_pin.sym} 1085 -665 0 1 {name=p6 sig_type=std_logic lab=vdd}
 C {gnd.sym} 1085 -530 0 0 {name=l18 lab=GND}
-C {sg13g2_pr/sg13_lv_nmos.sym} 150 -560 2 0 {name=M2
+C {sg13g2_pr/sg13_lv_nmos.sym} 150 -560 2 0 {name=M1
 l=5u
 w=7.14u
 ng=4
@@ -237,7 +237,7 @@ m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
-C {sg13g2_pr/sg13_lv_nmos.sym} 410 -560 2 1 {name=M3
+C {sg13g2_pr/sg13_lv_nmos.sym} 410 -560 2 1 {name=M2
 l=5u
 w=21u
 ng=8
@@ -246,7 +246,7 @@ model=sg13_lv_nmos
 spiceprefix=X
 }
 C {gnd.sym} 280 -430 0 0 {name=l3 lab=GND}
-C {sg13g2_pr/sg13_lv_pmos.sym} 150 -870 0 1 {name=M5
+C {sg13g2_pr/sg13_lv_pmos.sym} 150 -870 0 1 {name=M3
 l=5u
 w=15u
 ng=8
@@ -254,7 +254,7 @@ m=1
 model=sg13_lv_pmos
 spiceprefix=X
 }
-C {sg13g2_pr/sg13_lv_pmos.sym} 410 -870 0 0 {name=M1
+C {sg13g2_pr/sg13_lv_pmos.sym} 410 -870 0 0 {name=M4
 l=5u
 w=15u
 ng=8
@@ -266,7 +266,7 @@ C {lab_pin.sym} 280 -965 0 1 {name=p2 sig_type=std_logic lab=vdd}
 C {lab_pin.sym} 230 -740 3 0 {name=p3 sig_type=std_logic lab=v-}
 C {lab_pin.sym} 315 -740 0 0 {name=p8 sig_type=std_logic lab=v+}
 C {lab_pin.sym} 285 -870 1 1 {name=p9 sig_type=std_logic lab=Vo1}
-C {sg13g2_pr/sg13_lv_pmos.sym} 615 -870 0 0 {name=M4
+C {sg13g2_pr/sg13_lv_pmos.sym} 615 -870 0 0 {name=M5
 l=5u
 w=16u
 ng=8