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@ -19,7 +19,7 @@ After following the installation steps, you should be able to launch Xschem by e
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xschem
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Upon launching, the initial Xschem window should appear as follows:
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<p align="center"> <img src="../../media/Pasted image 20241017155312.png" width="800" height="400" /> </p>
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<p align="center"> <img src="../../media/module_0/main_menu.png" width="800" height="400" /> </p>
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This view includes test cases within the IHP PDK, demonstrating different types of simulations. Below is an overview of each type:
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@ -32,7 +32,7 @@ This view includes test cases within the IHP PDK, demonstrating different types
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The simulation library allows you to explore different designs and understand the simulation setups, which will be covered in detail throughout the course. To get started, try opening dc_lv_nmos by selecting the instance and pressing e. This will open the schematic view.
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From here, navigate to the "netlist" button in the top-right corner, then press "simulate." Your first schematic simulation in Xschem will now be complete. View the results by left-clicking the green arrow while holding down Ctrl. The output should look like this:
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<p align="center"> <img src="../../media/Pasted image 20241017162220.png" width="800" height="400" /> </p>
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<p align="center"> <img src="../../module_0/dc_sim.png" width="800" height="400" /> </p>
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If the dark mode theme is hard to read, you can toggle it by pressing "Shift + O."
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@ -142,7 +142,7 @@ Now you should conncect the bulk of the devices to the sources with a wire, by p
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From here you should connect the individual components so you have the same setup as seen in the following image:
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<p align="center"> <img src="../../media/setup_1.png" width="950" height="500" /> </p>
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<p align="center"> <img src="../../media/module_0/setup_1.png" width="950" height="500" /> </p>
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Next up we want to write the code for our simulation. Chose one of the code_shown blocks and press Q. In here change the name to NGSPICE and set only_toplevel to true. In the value section, insert the following code:
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@ -12,7 +12,7 @@ $$V_{BE} = V_T \cdot ln(\frac{I_C}{I_S})$$
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Where $I_C$ is the collector current and $I_S$ is the saturation current.
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The theory behind different circuit topology regarding the bandgap references are quite comprehensive, and will therefore not be covered here. Instead the circuit seen below is proposed:
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<p align="center"> <img src="../../media/Screenshot 2024-10-29 120123.png" width="800" height="700" /> </p>
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<p align="center"> <img src="../../media/module_1/bandgap_circuit.png" width="800" height="700" /> </p>
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From the following criteria, $I_{C,Q1}=I_{C,Q2}$ if $R_2 = R_3$, we can try to understand the circuit functionality. The voltage X and Y is forced to be equal due to the operation of the feedback of the OP-amps. This means that we can write the following expression
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@ -0,0 +1,43 @@
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# Bandgap design
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In integrated circuit (IC) design many circuits require a fixed stable, temperature independent voltage fixation in order to have a constant voltage reference.
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The use case for these stable references, could be used to provide a stable reference to data converters or bias operating points. These circuits is also called Bandgap References or in short BGR.
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They work by summing a proportional to absolute temperature device with a complementary proportional to absolute temperature device together, or in other words: The bandgap reference is comprised of two
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devices with opposite temperature coefficients within a given interval of interest.
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One of devices that exhibits inherent negative TC s is the bipolar junction transistor (BJT). The relation of the base to emitter voltage can be described with the following equation given as:
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$$V_{BE} = V_T \cdot ln(\frac{I_C}{I_S})$$
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Where $I_C$ is the collector current and $I_S$ is the saturation current.
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The theory behind different circuit topology regarding the bandgap references are quite comprehensive, and will therefore not be covered here. Instead the circuit seen below is proposed:
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<p align="center"> <img src="../../media/Screenshot 2024-10-29 120123.png" width="800" height="700" /> </p>
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From the following criteria, $I_{C,Q1}=I_{C,Q2}$ if $R_2 = R_3$, we can try to understand the circuit functionality. The voltage X and Y is forced to be equal due to the operation of the feedback of the OP-amps. This means that we can write the following expression
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$$\vert V_{BE1}\vert = \vert V_{BE2}\vert + I_{C2}\cdot R_1$$
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Making a simple KCL at node Y, shows that the current through $R_1$ must be given as
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$$I_{C2} = \frac{\vert V_{BE1} \vert - \vert V_{BE2} \vert }{R_1}$$
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$$I_{C2} = \frac{\left\vert V_T \cdot ln(\frac{I_{C1}}{I_{S1}})-V_T \cdot ln(n\cdot \frac{I_{C2}}{I_{S2}})\right\vert}{R_1}$$
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Now we know that $I_{C1} = I_{C2}$ , and $I_{S1} = I_{S2}$ . This gives the following expression for $I_{C2}$
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$$I_{C2} = \frac{V_T \cdot ln(n)}{R_1}$$
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Now we see we can describe the whole current in the branch of M4 as
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$$I_{D4} = \frac{\vert V_{BE1}\vert}{R_2} + \frac{V_T \cdot ln (n)}{R_1}$$
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In order to then set the bandgap voltage, the current is then copied out to the branch with the resistor $R_4$ and the relation can then be described by
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$$V_{out} = I_{D4} \cdot R_4 = \frac{R_4}{R_2} \cdot \left(\vert V_{BE1}\vert + \frac{R_2}{R_1} V_T \cdot ln(n)\right) $$
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So to sum up the operation we see that the bandgap voltage is given as a upscaling of the PTAT of the BJT given by the ratio of discrete resistors. Without this upscaling the sizes of the BJT would be incredibly large and low voltage reference wouldn't be possible. We highly recommend the reader to dive into the theory behind this literature, specified in the bibliography of this chapter
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# Bibliography
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- B. Razavi,“Design of Analog CMOS Integrated Circuits,” McGrawHill, second edition, Chapter 12
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- Ali Hajimiri lectures: https://www.youtube.com/watch?v=AMgrGvzCTck
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@ -0,0 +1,112 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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G {}
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||||
K {}
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V {}
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||||
S {}
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E {}
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||||
N 575 -200 575 -170 {
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lab=v+}
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N 655 -200 655 -170 {
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lab=v-}
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N 735 -200 735 -170 {
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lab=vdd}
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N 735 -110 735 -90 {
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lab=GND}
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N 655 -90 735 -90 {
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lab=GND}
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N 655 -110 655 -90 {
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lab=GND}
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N 575 -90 655 -90 {
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||||
lab=GND}
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||||
N 575 -110 575 -90 {
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lab=GND}
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||||
N 655 -90 655 -70 {
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lab=GND}
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N 345 -300 345 -280 {
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lab=GND}
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N 345 -445 345 -430 {
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lab=vdd}
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N 190 -405 210 -405 {
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lab=v+}
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N 190 -320 210 -320 {
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lab=v-}
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N 260 -275 260 -215 {
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lab=#net1}
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N 310 -195 310 -140 {
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lab=GND}
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N 260 -155 260 -140 {
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lab=GND}
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N 295 -285 310 -285 {
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lab=#net2}
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N 310 -285 310 -255 {
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lab=#net2}
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N 510 -365 620 -365 {
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lab=vout}
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N 555 -305 555 -290 {
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lab=GND}
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N 510 -365 515 -65 {
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lab=vout}
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N 330 -65 515 -65 {
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lab=vout}
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N 210 -65 275 -65 {
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lab=v-}
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N 210 -320 210 -65 {
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lab=v-}
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N 210 -5 210 5 {
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lab=GND}
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C {two_stage_OTA.sym} 360 -365 0 0 {name=x1}
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C {vsource.sym} 575 -140 0 0 {name=V1 value= 0.6 AC 1
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}
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C {vsource.sym} 655 -140 0 0 {name=V2 value= 0.6 AC 1}
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C {vsource.sym} 735 -140 0 0 {name=VDD value=1.2}
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C {gnd.sym} 655 -70 0 0 {name=l1 lab=GND}
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C {gnd.sym} 345 -280 0 0 {name=l2 lab=GND}
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C {lab_pin.sym} 345 -445 0 0 {name=p1 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 735 -200 0 0 {name=p2 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 575 -200 0 0 {name=p3 sig_type=std_logic lab=v+}
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C {lab_pin.sym} 655 -200 0 0 {name=p4 sig_type=std_logic lab=v-}
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C {lab_pin.sym} 190 -405 0 0 {name=p5 sig_type=std_logic lab=v+}
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C {lab_pin.sym} 190 -320 0 0 {name=p6 sig_type=std_logic lab=v-}
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C {isource.sym} 260 -185 0 0 {name=I0 value=2.78u}
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C {isource.sym} 310 -225 0 0 {name=I1 value=6.28u}
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C {gnd.sym} 260 -140 0 0 {name=l3 lab=GND}
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C {gnd.sym} 310 -140 0 0 {name=l4 lab=GND}
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C {capa.sym} 555 -335 0 0 {name=Cload
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m=1
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value=1p
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 555 -290 0 0 {name=l5 lab=GND}
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C {iopin.sym} 620 -365 0 0 {name=p7 lab=vout}
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C {devices/code_shown.sym} -340 -190 0 0 {name=MODEL only_toplevel=true
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format="tcleval( @value )"
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value="
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.lib cornerMOSlv.lib mos_tt
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"}
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C {devices/code_shown.sym} -365 -515 0 0 {name=NGSPICE only_toplevel=true
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value="
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.control
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op
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ac dec 20 1 1e9
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save all
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let Av = db(v(vout))
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write output_file.raw
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.endc
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"}
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C {devices/code_shown.sym} -385 -300 0 0 {name=MODEL1 only_toplevel=true
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format="tcleval( @value )"
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value="
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.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
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"}
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C {ind.sym} 300 -65 3 1 {name=L6
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m=1
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value=100
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footprint=1206
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device=inductor}
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C {capa.sym} 210 -35 0 0 {name=C1
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m=1
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value=100
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 210 5 0 0 {name=l7 lab=GND}
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@ -0,0 +1,58 @@
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/ota_testbench.sch
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**.subckt ota_testbench vout
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*.iopin vout
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x1 vdd net1 net2 v+ v- vout GND two_stage_OTA
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V1 v+ GND 0.6
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V2 v- GND 0.6
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VDD vdd GND 1.2
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I0 net1 GND 2.78u
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I1 net2 GND 6.28u
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Cload vout GND 1p m=1
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L6 v- vout 100 m=1
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C1 v- GND 100 m=1
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**** begin user architecture code
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.lib cornerMOSlv.lib mos_tt
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.control
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op
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ac dec 20 1 1e9
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save all
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let Av = db(v(vout))
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write output_file.raw
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.endc
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.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ
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**** end user architecture code
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**.ends
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* expanding symbol: two_stage_OTA.sym # of pins=7
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** sym_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
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.subckt two_stage_OTA vdd itail iout v+ v- vout vss
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*.iopin v-
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*.iopin v+
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*.iopin itail
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*.iopin vss
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*.iopin vdd
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*.iopin iout
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*.iopin vout
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XM4 net3 net1 vss vss sg13_lv_nmos w=0.50u l=9.75u ng=1 m=1
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XM3 net1 net1 vss vss sg13_lv_nmos w=0.50u l=9.75u ng=1 m=1
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XM1 net1 v- net2 vdd sg13_lv_pmos w=6.96u l=3.25u ng=4 m=1
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XM2 net3 v+ net2 vdd sg13_lv_pmos w=6.96u l=3.25u ng=4 m=1
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XM5 net2 itail vdd vdd sg13_lv_pmos w=3u l=130n ng=1 m=1
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XM8 itail itail vdd vdd sg13_lv_pmos w=3u l=130n ng=1 m=1
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XM7 vout iout vdd vdd sg13_lv_pmos w=3.6525u l=3.38u ng=4 m=1
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XM9 iout iout vdd vdd sg13_lv_pmos w=3.6525u l=3.38u ng=4 m=1
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XC1 net3 vout cap_cmim w=9.98e-6 l=7.7e-6 m=4
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XM6 vout net3 vss vss sg13_lv_nmos w=2.28u l=9.75u ng=1 m=1
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.ends
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.GLOBAL GND
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.end
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File diff suppressed because one or more lines are too long
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@ -0,0 +1,22 @@
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/xschem/two_stage_OTA.sch
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**.subckt two_stage_OTA v- v+ itail vdd vss vdd iout vout
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*.iopin v-
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*.iopin v+
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*.iopin itail
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*.iopin vdd
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*.iopin vss
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*.iopin vdd
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*.iopin iout
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*.iopin vout
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XM4 net3 net1 vss vss sg13_lv_nmos w=0.50u l=9.75u ng=1 m=1
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XM3 net1 net1 vss vss sg13_lv_nmos w=0.50u l=9.75u ng=1 m=1
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XM1 net1 v- net2 vdd sg13_lv_pmos w=6.96u l=3.25u ng=4 m=1
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XM2 net3 v+ net2 vdd sg13_lv_pmos w=6.96u l=3.25u ng=4 m=1
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XM5 net2 itail vdd vdd sg13_lv_pmos w=3u l=130n ng=1 m=1
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XM8 itail itail vdd vdd sg13_lv_pmos w=3u l=130n ng=1 m=1
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XM7 vout bias vdd vdd sg13_lv_pmos w=3.6525u l=3.38u ng=4 m=1
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XM9 iout iout vdd vdd sg13_lv_pmos w=3.6525u l=3.38u ng=4 m=1
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XC1 net3 vout cap_cmim w=9.98e-6 l=7.7e-6 m=4
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XM6 vout net3 vss vss sg13_lv_nmos w=2.28u l=9.75u ng=1 m=1
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**.ends
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.end
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@ -0,0 +1,195 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 440 -280 440 -240 {
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lab=#net1}
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N 440 -280 550 -280 {
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lab=#net1}
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N 440 -150 650 -150 {
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lab=vss}
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N 440 -210 440 -150 {
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lab=vss}
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N 550 -210 610 -210 {
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lab=#net1}
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N 550 -280 550 -210 {
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lab=#net1}
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N 480 -210 550 -210 {
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lab=#net1}
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||||
N 650 -210 650 -150 {
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lab=vss}
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N 440 -340 440 -280 {
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lab=#net1}
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N 440 -370 650 -370 {
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lab=vdd}
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N 440 -420 440 -400 {
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lab=#net2}
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N 650 -420 650 -400 {
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lab=#net2}
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N 550 -420 650 -420 {
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||||
lab=#net2}
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N 370 -370 400 -370 {
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lab=v-}
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N 690 -370 720 -370 {
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lab=v+}
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N 400 -470 510 -470 {
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lab=itail}
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N 350 -520 350 -470 {
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lab=vdd}
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N 350 -440 350 -420 {
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||||
lab=itail}
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N 350 -420 400 -420 {
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lab=itail}
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N 400 -470 400 -420 {
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lab=itail}
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N 390 -470 400 -470 {
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lab=itail}
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N 350 -420 350 -400 {
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lab=itail}
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N 160 -420 160 -400 {
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lab=iout}
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N 160 -420 210 -420 {
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lab=iout}
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||||
N 210 -470 230 -470 {
|
||||
lab=iout}
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N 160 -520 160 -470 {
|
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lab=vdd}
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N 160 -440 160 -420 {
|
||||
lab=iout}
|
||||
N 210 -470 210 -420 {
|
||||
lab=iout}
|
||||
N 200 -470 210 -470 {
|
||||
lab=iout}
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N 790 -470 810 -470 {
|
||||
lab=bias}
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||||
N 740 -270 750 -270 {
|
||||
lab=#net3}
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||||
N 650 -270 650 -240 {
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||||
lab=#net3}
|
||||
N 850 -520 850 -470 {
|
||||
lab=vdd}
|
||||
N 850 -270 850 -240 {
|
||||
lab=vout}
|
||||
N 810 -270 850 -270 {
|
||||
lab=vout}
|
||||
N 850 -370 850 -270 {
|
||||
lab=vout}
|
||||
N 740 -270 740 -210 {
|
||||
lab=#net3}
|
||||
N 740 -210 810 -210 {
|
||||
lab=#net3}
|
||||
N 850 -370 890 -370 {
|
||||
lab=vout}
|
||||
N 850 -440 850 -370 {
|
||||
lab=vout}
|
||||
N 650 -270 740 -270 {
|
||||
lab=#net3}
|
||||
N 650 -340 650 -270 {
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||||
lab=#net3}
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||||
N 650 -150 850 -150 {
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||||
lab=vss}
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||||
N 550 -520 850 -520 {
|
||||
lab=vdd}
|
||||
N 160 -520 350 -520 {
|
||||
lab=vdd}
|
||||
N 550 -520 550 -470 {
|
||||
lab=vdd}
|
||||
N 350 -520 550 -520 {
|
||||
lab=vdd}
|
||||
N 550 -440 550 -420 {
|
||||
lab=#net2}
|
||||
N 440 -420 550 -420 {
|
||||
lab=#net2}
|
||||
N 850 -210 850 -150 {
|
||||
lab=vss}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 630 -210 2 1 {name=M4
|
||||
l=9.75u
|
||||
w=0.50u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 460 -210 2 0 {name=M3
|
||||
l=9.75u
|
||||
w=0.50u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 420 -370 0 0 {name=M1
|
||||
l=3.25u
|
||||
w=6.96u
|
||||
ng=4
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 670 -370 0 1 {name=M2
|
||||
l=3.25u
|
||||
w=6.96u
|
||||
ng=4
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 530 -470 0 0 {name=M5
|
||||
l=130n
|
||||
w=3u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 370 -470 0 1 {name=M8
|
||||
l=130n
|
||||
w=3u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -470 0 0 {name=M7
|
||||
l=3.38u
|
||||
w=3.6525u
|
||||
ng=4
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/sg13_lv_pmos.sym} 180 -470 0 1 {name=M9
|
||||
l=3.38u
|
||||
w=3.6525u
|
||||
ng=4
|
||||
m=1
|
||||
model=sg13_lv_pmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {sg13g2_pr/cap_cmim.sym} 780 -270 3 0 {name=C1
|
||||
model=cap_cmim
|
||||
w=9.98e-6
|
||||
l=7.7e-6
|
||||
m=4
|
||||
spiceprefix=X}
|
||||
C {sg13g2_pr/sg13_lv_nmos.sym} 830 -210 2 1 {name=M6
|
||||
l=9.75u
|
||||
w=2.28u
|
||||
ng=1
|
||||
m=1
|
||||
model=sg13_lv_nmos
|
||||
spiceprefix=X
|
||||
}
|
||||
C {iopin.sym} 370 -370 0 1 {name=p10 lab=v-}
|
||||
C {iopin.sym} 720 -370 0 0 {name=p11 lab=v+}
|
||||
C {iopin.sym} 350 -400 0 1 {name=p4 lab=itail}
|
||||
C {iopin.sym} 550 -150 1 1 {name=p5 lab=vss}
|
||||
C {iopin.sym} 550 -520 1 1 {name=p1 lab=vdd}
|
||||
C {iopin.sym} 160 -400 0 1 {name=p3 lab=iout}
|
||||
C {iopin.sym} 890 -370 0 0 {name=p8 lab=vout}
|
||||
C {lab_pin.sym} 230 -470 0 1 {name=p7 sig_type=std_logic lab=iout}
|
||||
C {lab_pin.sym} 790 -470 0 0 {name=p6 sig_type=std_logic lab=iout}
|
||||
C {lab_pin.sym} 550 -370 3 0 {name=p2 sig_type=std_logic lab=vdd}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
v {xschem version=3.4.5 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {type=subcircuit
|
||||
format="@name @pinlist @symname"
|
||||
template="name=x1"
|
||||
}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
L 4 -130 -80 130 0 {}
|
||||
L 4 -130 80 130 0 {}
|
||||
L 4 -130 -80 -130 80 {}
|
||||
L 7 -15 -65 -15 -45 {}
|
||||
L 7 -100 70 -100 90 {}
|
||||
L 7 -65 60 -65 80 {}
|
||||
L 7 -150 -40 -130 -40 {}
|
||||
L 7 -150 45 -130 45 {}
|
||||
L 7 130 0 150 0 {}
|
||||
L 7 -15 45 -15 65 {}
|
||||
B 5 -17.5 -67.5 -12.5 -62.5 {name=vdd dir=inout}
|
||||
B 5 -102.5 87.5 -97.5 92.5 {name=itail dir=inout}
|
||||
B 5 -67.5 77.5 -62.5 82.5 {name=iout dir=inout}
|
||||
B 5 -152.5 -42.5 -147.5 -37.5 {name=v+ dir=inout}
|
||||
B 5 -152.5 42.5 -147.5 47.5 {name=v- dir=inout}
|
||||
B 5 147.5 -2.5 152.5 2.5 {name=vout dir=inout}
|
||||
B 5 -17.5 62.5 -12.5 67.5 {name=vss dir=inout}
|
||||
T {@2stage_OTA} -76.5 -16 0 0 0.3 0.3 {}
|
||||
T {@name} 40 -52 0 0 0.2 0.2 {}
|
||||
T {vdd} -19 -40 3 1 0.2 0.2 {}
|
||||
T {itail} -96 65 1 1 0.2 0.2 {}
|
||||
T {iout} -61 55 1 1 0.2 0.2 {}
|
||||
T {v+} -125 -44 0 0 0.2 0.2 {}
|
||||
T {v-} -125 41 0 0 0.2 0.2 {}
|
||||
T {vout} 110 -9 0 1 0.2 0.2 {}
|
||||
T {vss} -11 40 1 1 0.2 0.2 {}
|
||||
|
|
@ -2,14 +2,14 @@
|
|||
"cells": [
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 429,
|
||||
"execution_count": 1,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": [
|
||||
"import numpy as np\n",
|
||||
"#for windows\n",
|
||||
"import sys\n",
|
||||
"sys.path.append(r'C:\\Users\\pedersen\\gmid') # path to gmid repository\n",
|
||||
"#import sys\n",
|
||||
"#sys.path.append(r'C:\\Users\\pedersen\\gmid') # path to gmid repository\n",
|
||||
"# ------\n",
|
||||
"import matplotlib.pyplot as plt\n",
|
||||
"from mosplot import load_lookup_table, LoadMosfet # make sure that mosplot can be found in the python path\n",
|
||||
|
|
@ -21,12 +21,12 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 430,
|
||||
"execution_count": 2,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": [
|
||||
"pmos_lv_path = r'C:\\Users\\pedersen\\Desktop\\OpenDesingCourse\\no_touch_files\\gmoveridpypmos_gmid_final.npy'\n",
|
||||
"nmos_lv_path =r'C:\\Users\\pedersen\\Desktop\\OpenDesingCourse\\no_touch_files\\gmoveridpynmos_final_gmid.npy'\n",
|
||||
"pmos_lv_path = '/home/pedersen/chipdesign/cmos_analog/gmid_sweeps/pmos_lv_sweep.npy'\n",
|
||||
"nmos_lv_path = '/home/pedersen/chipdesign/cmos_analog/gmid_sweeps/nmos_lv_sweep.npy'\n",
|
||||
"\n",
|
||||
"lookup_table_pmos = load_lookup_table(pmos_lv_path)\n",
|
||||
"lookup_table_nmos = load_lookup_table(nmos_lv_path)"
|
||||
|
|
@ -34,17 +34,17 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 431,
|
||||
"execution_count": 3,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": [
|
||||
"nmos = LoadMosfet(lookup_table=lookup_table_nmos, mos=\"nmos\", vsb=0.0, vds=0.6)\n",
|
||||
"pmos = LoadMosfet(lookup_table=lookup_table_pmos, mos=\"pmos\", vsb=0, vds=-0.6, vgs=(-1.2, -0.1))"
|
||||
"pmos = LoadMosfet(lookup_table=lookup_table_pmos, mos=\"pmos\", vsb=-0.2, vds=-0.6, vgs=(-1.2, -0.1))"
|
||||
]
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 432,
|
||||
"execution_count": 4,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": [
|
||||
|
|
@ -237,7 +237,7 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 434,
|
||||
"execution_count": 5,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": [
|
||||
|
|
@ -259,13 +259,13 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 435,
|
||||
"execution_count": 6,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "7885bed517d544a6a5186b585b73be1c",
|
||||
"model_id": "32c41670fdbd48cd915f8cecbdd4fc9c",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -290,9 +290,20 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 436,
|
||||
"execution_count": 26,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"outputs": [
|
||||
{
|
||||
"data": {
|
||||
"text/plain": [
|
||||
"6.283185307179587e-06"
|
||||
]
|
||||
},
|
||||
"execution_count": 26,
|
||||
"metadata": {},
|
||||
"output_type": "execute_result"
|
||||
}
|
||||
],
|
||||
"source": [
|
||||
"# For max gmro and vgs of 0.6V we have gmid of 5\n",
|
||||
"L_M6 = 9.75e-6\n",
|
||||
|
|
@ -300,12 +311,13 @@
|
|||
"gm_M6 = 2*np.pi*GBW*Cl # we have se\n",
|
||||
"id_outputstage = gm_M6/gmid_M6\n",
|
||||
"gmro_M6 = 55.68\n",
|
||||
"ro_M6 = gmro_M6/gm_M6\n"
|
||||
"ro_M6 = gmro_M6/gm_M6\n",
|
||||
"id_outputstage"
|
||||
]
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 437,
|
||||
"execution_count": 27,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -329,13 +341,13 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 438,
|
||||
"execution_count": 28,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "36da585aea1b4f0bb5722f07a41fc809",
|
||||
"model_id": "e631757f58a64118873cc3240a08af73",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -360,7 +372,7 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 439,
|
||||
"execution_count": 29,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": [
|
||||
|
|
@ -370,7 +382,7 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 440,
|
||||
"execution_count": 30,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -393,13 +405,13 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 441,
|
||||
"execution_count": 31,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "b0beb804bcf4452593b1eb60e6baed9d",
|
||||
"model_id": "f4c661be0d36403b8737fd91a618fdc7",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -413,7 +425,7 @@
|
|||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "0fc744fa24c34ef7a0d5b5590746f95c",
|
||||
"model_id": "b2595dde5ebe43f3be4544582bafe044",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -432,7 +444,7 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 442,
|
||||
"execution_count": 32,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -502,7 +514,7 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 443,
|
||||
"execution_count": 33,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -511,7 +523,7 @@
|
|||
"1.392e-06"
|
||||
]
|
||||
},
|
||||
"execution_count": 443,
|
||||
"execution_count": 33,
|
||||
"metadata": {},
|
||||
"output_type": "execute_result"
|
||||
}
|
||||
|
|
@ -522,13 +534,13 @@
|
|||
"gmid_M34 = 5\n",
|
||||
"Rout1 = 8e6\n",
|
||||
"gm_M34 = gmro_M34_assumption/Rout1\n",
|
||||
"id_outputstage = gm_M34/gmid_M34\n",
|
||||
"id_outputstage"
|
||||
"id_branch = gm_M34/gmid_M34\n",
|
||||
"id_branch"
|
||||
]
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 444,
|
||||
"execution_count": 34,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -544,7 +556,7 @@
|
|||
"gm_M12 = dB_to_linear(float(Av_wish-Av2_db))/Rout1\n",
|
||||
"CC = 1/(2*np.pi*fdominant* Rout1 * (1 + Av2))\n",
|
||||
"gmro_M12 = gm_M12 * Rout1*3\n",
|
||||
"gmid_M12 = gm_M12/id_outputstage\n",
|
||||
"gmid_M12 = gm_M12/id_branch\n",
|
||||
"print(f'gmro_M12 = {gmro_M12:.2f}')\n",
|
||||
"print(f'gmid_M12 = {gmid_M12:.2f}')"
|
||||
]
|
||||
|
|
@ -558,13 +570,13 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 445,
|
||||
"execution_count": 35,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "1a84ed5efc7d45a490772af3f76341ee",
|
||||
"model_id": "265f7ede0fd44c63a8c32143dc694ea6",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -578,7 +590,7 @@
|
|||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "1909ac8e35914a33aee50aedb2a86205",
|
||||
"model_id": "6b273b07c2044c82997f264b866c199d",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -591,7 +603,7 @@
|
|||
}
|
||||
],
|
||||
"source": [
|
||||
"pmos_M12 = LoadMosfet(lookup_table=lookup_table_pmos, mos=\"pmos\", vsb=0, vds=-0.6, vgs=(-1.2, -0.1))\n",
|
||||
"pmos_M12 = LoadMosfet(lookup_table=lookup_table_pmos, mos=\"pmos\", vsb=-0.2, vds=-0.6, vgs=(-1.2, -0.1))\n",
|
||||
"nmos_M34 = LoadMosfet(lookup_table=lookup_table_nmos, mos=\"nmos\", vsb=0, vds=0.6)\n",
|
||||
"\n",
|
||||
"id_values_M12 = pmos_M12.extracted_table['id']\n",
|
||||
|
|
@ -604,20 +616,20 @@
|
|||
"gds_values_M34 = nmos_M34.extracted_table['gds']\n",
|
||||
"vgs_values_M34 = nmos_M34.extracted_table['vgs']\n",
|
||||
"\n",
|
||||
"plot_data_vs_data(gm_values_M12/id_values_M12, gm_values_M12/gds_values_M12, vgs_values_M12, pmos_M12.extracted_table['lengths'], 'gm/id', 'm12 gm/gds', log=True)\n",
|
||||
"plot_data_vs_data(gm_values_M34/id_values_M34, gm_values_M34/gds_values_M34, vgs_values_M34, nmos_M34.extracted_table['lengths'], 'gm/id', 'm34 gm/gds', log=True)"
|
||||
"plot_data_vs_data(gm_values_M12/id_values_M12, gm_values_M12/gds_values_M12, vgs_values_M12, pmos_M12.extracted_table['lengths'], 'gm/id', 'm12 gm/gds')\n",
|
||||
"plot_data_vs_data(gm_values_M34/id_values_M34, gm_values_M34/gds_values_M34, vgs_values_M34, nmos_M34.extracted_table['lengths'], 'gm/id', 'm34 gm/gds')"
|
||||
]
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 446,
|
||||
"execution_count": 36,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
"name": "stdout",
|
||||
"output_type": "stream",
|
||||
"text": [
|
||||
"L_M12 = 3.38e-06\n",
|
||||
"L_M12 = 3.25e-06\n",
|
||||
"gmid_M12 = 21.50\n",
|
||||
"L_M34 = 9.75e-06\n",
|
||||
"gmid_M34 = 5.00\n"
|
||||
|
|
@ -625,7 +637,7 @@
|
|||
}
|
||||
],
|
||||
"source": [
|
||||
"L_M12 = 3.38e-6\n",
|
||||
"L_M12 = 3.25e-6\n",
|
||||
"L_M34 = 9.75e-6\n",
|
||||
"\n",
|
||||
"print(f'L_M12 = {L_M12:.2e}')\n",
|
||||
|
|
@ -637,13 +649,13 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 447,
|
||||
"execution_count": 37,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "6907db96f53d4e378c57942f9be804a3",
|
||||
"model_id": "f996f78202ee479ba9ce8043d3049f46",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -657,7 +669,7 @@
|
|||
{
|
||||
"data": {
|
||||
"application/vnd.jupyter.widget-view+json": {
|
||||
"model_id": "b9ee6f9f9f54489796067b7b5209ab57",
|
||||
"model_id": "18906fc315ab406b8bfd655e76f2e299",
|
||||
"version_major": 2,
|
||||
"version_minor": 0
|
||||
},
|
||||
|
|
@ -679,7 +691,7 @@
|
|||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 448,
|
||||
"execution_count": 40,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -689,28 +701,28 @@
|
|||
"\n",
|
||||
"Input Stage Amplification Summary\n",
|
||||
"Width and Lengths for M12\n",
|
||||
" W = 34.80 um\n",
|
||||
" L = 3.38 um\n",
|
||||
" W = 27.84 um\n",
|
||||
" L = 3.25 um\n",
|
||||
"Inversion Region for M12: Weak Inversion\n",
|
||||
"Width and Lengths for M34\n",
|
||||
" W = 0.50 um\n",
|
||||
" L = 9.75 um\n",
|
||||
"Inversion Region for M34: Strong Inversion\n",
|
||||
"Input Stage Bias:\n",
|
||||
" Output Current : 1.39 μA\n",
|
||||
" Output tail current: 2.78 μA\n",
|
||||
" Branch Current : 1.39 μA\n",
|
||||
" input Tail current: 2.78 μA\n",
|
||||
"\n"
|
||||
]
|
||||
}
|
||||
],
|
||||
"source": [
|
||||
"id_over_W_M12 = 0.04\n",
|
||||
"id_over_W_M12 = 0.05\n",
|
||||
"id_over_W_M34 = 2.76\n",
|
||||
"\n",
|
||||
"display_outcurrent, unit_outcurrent = display_current(id_outputstage)\n",
|
||||
"display_id_branch, unit_id_branch = display_current(id_branch)\n",
|
||||
"\n",
|
||||
"W_M12 = id_outputstage/id_over_W_M12\n",
|
||||
"W_M34 = id_outputstage/id_over_W_M34\n",
|
||||
"W_M12 = id_branch/id_over_W_M12\n",
|
||||
"W_M34 = id_branch/id_over_W_M34\n",
|
||||
"\n",
|
||||
"\n",
|
||||
"input_stage_summary = f\"\"\"\n",
|
||||
|
|
@ -724,15 +736,15 @@
|
|||
" L = {L_M34*1e6:.2f} um\n",
|
||||
"Inversion Region for M34: {determine_inversion_region(gmid_M34, 'nmos')}\n",
|
||||
"Input Stage Bias:\n",
|
||||
" Output Current : {display_outcurrent:.2f} {unit_outcurrent}\n",
|
||||
" Output tail current: {display_outcurrent*2:.2f} {unit_outcurrent}\n",
|
||||
" Branch Current : {display_id_branch:.2f} {unit_id_branch}\n",
|
||||
" input Tail current: {display_id_branch*2:.2f} {unit_id_branch}\n",
|
||||
"\"\"\"\n",
|
||||
"print(input_stage_summary)"
|
||||
]
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": 451,
|
||||
"execution_count": 44,
|
||||
"metadata": {},
|
||||
"outputs": [
|
||||
{
|
||||
|
|
@ -765,16 +777,16 @@
|
|||
" \n",
|
||||
"Input Stage Amplification Summary\n",
|
||||
"Width and Lengths for M12\n",
|
||||
" W = 34.80 um\n",
|
||||
" L = 3.38 um\n",
|
||||
" W = 27.84 um\n",
|
||||
" L = 3.25 um\n",
|
||||
"Inversion Region for M12: Weak Inversion\n",
|
||||
"Width and Lengths for M34\n",
|
||||
" W = 0.50 um\n",
|
||||
" L = 9.75 um\n",
|
||||
"Inversion Region for M34: Strong Inversion\n",
|
||||
"Input Stage Bias:\n",
|
||||
" Output Current : 1.39 μA\n",
|
||||
" Output tail current: 2.78 μA\n",
|
||||
" Branch Current : 1.39 μA\n",
|
||||
" input Tail current: 2.78 μA\n",
|
||||
"\n",
|
||||
"\n",
|
||||
"Gain and frequency response:\n",
|
||||
|
|
@ -825,11 +837,32 @@
|
|||
"\"\"\"\n",
|
||||
"print(summary)"
|
||||
]
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": null,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": []
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": null,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": []
|
||||
},
|
||||
{
|
||||
"cell_type": "code",
|
||||
"execution_count": null,
|
||||
"metadata": {},
|
||||
"outputs": [],
|
||||
"source": []
|
||||
}
|
||||
],
|
||||
"metadata": {
|
||||
"kernelspec": {
|
||||
"display_name": "Python 3",
|
||||
"display_name": "Python 3 (ipykernel)",
|
||||
"language": "python",
|
||||
"name": "python3"
|
||||
},
|
||||
|
|
@ -843,9 +876,9 @@
|
|||
"name": "python",
|
||||
"nbconvert_exporter": "python",
|
||||
"pygments_lexer": "ipython3",
|
||||
"version": "3.12.5"
|
||||
"version": "3.10.12"
|
||||
}
|
||||
},
|
||||
"nbformat": 4,
|
||||
"nbformat_minor": 2
|
||||
"nbformat_minor": 4
|
||||
}
|
||||
Loading…
Reference in New Issue