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IHP-AnalogAcademy
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change gitignore

This commit is contained in:
PhillipRambo 2025-04-10 09:37:14 +02:00
parent d5ba2495a2
commit ad1e063a90
4 changed files with 29 additions and 52 deletions
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1
.gitignore vendored
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@ -1,4 +1,5 @@
/misc/
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/python/
**/.vscode/
**/sar_logic_obj_dir/
**/.ipynb_checkpoints/

37
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/sar_logic_tb.sch
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@ -107,8 +107,9 @@ logy=0
color=4
node=en}
color="4 7"
node="en
rst"}
B 2 1580 -1670 2380 -1280 {flags=graph
y1=0
y2=1.3
@ -163,30 +164,7 @@ b4
b5
b6
b7"}
B 2 760 -1670 1560 -1280 {flags=graph
y1=0
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.0002
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
color=4
node=rst}
T {Analog} 960 -1020 0 0 0.4 0.4 {}
T {Analog} 350 -1130 0 0 0.4 0.4 {}
T {Digital} 770 -1010 0 0 0.4 0.4 {}
N 670 -680 730 -680 {
lab=#net1}
@ -208,8 +186,6 @@ N 590 -740 610 -740 {lab=Op}
N 590 -760 610 -760 {lab=clk}
N 670 -700 730 -700 {
lab=#net5}
N 610 -570 610 -540 {lab=clk_reserve}
N 610 -480 610 -470 {lab=GND}
N 1000 -930 1200 -930 {
lab=B5}
N 1000 -910 1200 -910 {lab=B4}
@ -257,7 +233,7 @@ N 1000 -510 1200 -510 {lab=D0}
N 890 -510 940 -510 {lab=#net27}
N 340 -720 340 -710 {lab=clk}
N 340 -650 340 -640 {lab=GND}
C {devices/code_shown.sym} 620 -1130 0 0 {name=NGSPICE only_toplevel=true
C {devices/code_shown.sym} 1250 -910 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.control
@ -350,9 +326,6 @@ C {devices/lab_pin.sym} 1200 -890 2 0 {name=p15 sig_type=std_logic lab=B3}
C {devices/lab_pin.sym} 1200 -910 2 0 {name=p16 sig_type=std_logic lab=B4}
C {devices/vsource.sym} 340 -1030 0 0 {name=V6 value="dc 0 ac 0 PULSE(1.2 0 100u 1n 1n 500u 1m)"}
C {devices/vsource.sym} 340 -550 0 0 {name=V2 value="dc 0 ac 0 PULSE(0 1.2 100u 1n 1n 10u 1m)"}
C {devices/vsource.sym} 610 -510 0 0 {name=V1 value="dc 0 ac 0 pulse(0 1 0 1n 1n 5n 10n)"}
C {devices/gnd.sym} 610 -470 0 0 {name=l3 lab=GND}
C {devices/lab_pin.sym} 610 -570 2 0 {name=p17 sig_type=std_logic lab=clk_reserve}
C {devices/lab_pin.sym} 590 -680 2 1 {name=p2 sig_type=std_logic lab=rst}
C {devices/lab_pin.sym} 590 -760 2 1 {name=p12 sig_type=std_logic lab=clk}
C {devices/vsource.sym} 340 -810 0 0 {name=V5 value="dc 0 ac 0 PULSE(0 1.2 100u 1n 1n 500u 1m)"}

16
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sch
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@ -143,13 +143,13 @@ m=1
spiceprefix=X}
C {sg13g2_pr/cap_cmim.sym} 610 -560 0 0 {name=C6
model=cap_cmim
w=11.485e-6
l=11.485e-6
w=9.39e-6
l=6.99e-6
m=1
spiceprefix=X}
C {sg13g2_pr/sg13_lv_nmos.sym} 1040 -530 3 1 {name=M8
l=0.13u
w=5u
w=3u
ng=1
m=1
model=sg13_lv_nmos
@ -157,7 +157,7 @@ spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 1150 -530 1 0 {name=M9
l=0.13u
w=5u
w=2.5u
ng=1
m=1
model=sg13_lv_nmos
@ -180,7 +180,7 @@ model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 590 -230 0 0 {name=M12
l=0.13u
l=0.4u
w=1.3u
ng=1
m=1
@ -227,6 +227,6 @@ w=4.665e-6
l=6.99e-6
m=1
spiceprefix=X}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 430 -250 3 0 {name=x1}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 1080 -720 0 1 {name=x2}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 960 -300 0 0 {name=x3}
C {inverter.sym} 430 -250 3 0 {name=x1}
C {inverter.sym} 1080 -720 0 1 {name=x2}
C {inverter.sym} 960 -300 0 0 {name=x3}

27
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/testbench/bootstrap_switch_tbs.sch
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@ -5,15 +5,15 @@ V {}
S {}
E {}
B 2 620 -870 1420 -470 {flags=graph
y1=-0.0041666666
y2=0.0058333334
y1=-0.033
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0.0010238745
x2=0.0024868745
x1=-0.00014753886
x2=0.00114631
divx=5
subdivx=1
xlabmag=1.0
@ -26,15 +26,15 @@ logx=0
logy=0
}
B 2 620 -460 1420 -60 {flags=graph
y1=0.00069444443
y2=0.010694444
y1=0
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0.0010238745
x2=0.0024868745
x1=-0.00014753886
x2=0.00114631
divx=5
subdivx=1
xlabmag=1.0
@ -60,7 +60,7 @@ N 360 -360 360 -290 {lab=vdd}
N 500 -340 500 -300 {lab=GND}
N 500 -430 500 -400 {lab=vo}
N 440 -430 500 -430 {lab=vo}
C {devices/code_shown.sym} 0 -80 0 0 {name=MODEL only_toplevel=true
C {devices/code_shown.sym} 10 -40 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value=".lib cornerMOSlv.lib mos_tt
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
@ -70,14 +70,17 @@ only_toplevel=true
value="
.control
save all
tran 100u 1.463m
tran 1u 1.024m
set wr_singlescale
set wr_vecnames
write test_bootstrap.raw
wrdata vout_data.txt v(vo)
.endc
" }
C {vsource.sym} 60 -370 0 0 {name=V1 value="PULSE(0 5 0 1n 1n 0.5u 1u)"}
C {vsource.sym} 60 -370 0 0 {name=V1 value="PULSE(0 5 0 10p 10p 0.5u 1u)"}
C {gnd.sym} 60 -320 0 1 {name=l2 lab=GND}
C {lab_pin.sym} 60 -430 0 0 {name=p1 sig_type=std_logic lab=clk}
C {vsource.sym} 60 -510 0 0 {name=V2 value="SIN(0.6 0.6 683 0 0 0)"}
C {vsource.sym} 60 -510 0 0 {name=V2 value="SIN(0.6 0.6 12.695e3 0 0 0)"}
C {gnd.sym} 60 -460 0 1 {name=l3 lab=GND}
C {lab_pin.sym} 60 -570 0 0 {name=p2 sig_type=std_logic lab=vin}
C {iopin.sym} 510 -430 0 0 {name=p3 lab=vo}