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This commit is contained in:
PhillipRambo 2025-04-08 11:27:04 +02:00
parent cb7042fae3
commit aad2182e39
124 changed files with 3438 additions and 6615 deletions
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48
modules/module_0_foundations/scripting/gmid_test.ipynb
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@ -2,7 +2,7 @@
"cells": [
{
"cell_type": "code",
"execution_count": 1,
"execution_count": 8,
"id": "fe26dc38-6623-48db-820a-cf131ac9a268",
"metadata": {},
"outputs": [
@ -28,7 +28,7 @@
},
{
"cell_type": "code",
"execution_count": 2,
"execution_count": 9,
"id": "9f325daf-eb3b-4cf7-8ffe-b9b94e7f66ea",
"metadata": {},
"outputs": [],
@ -43,7 +43,7 @@
},
{
"cell_type": "code",
"execution_count": 3,
"execution_count": 10,
"id": "b5b31aca-47bf-4461-8e50-16c20f03b337",
"metadata": {},
"outputs": [],
@ -58,7 +58,7 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 11,
"id": "743dc381-0d35-4aa9-847c-c42c80c17786",
"metadata": {},
"outputs": [],
@ -69,7 +69,7 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 12,
"id": "b27d5fca-3436-4df7-895f-f6a4bbd7a80d",
"metadata": {
"jupyter": {
@ -263,10 +263,25 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 13,
"id": "b7cc630f-b385-47a6-a6f9-ac0d10effffe",
"metadata": {},
"outputs": [],
"outputs": [
{
"data": {
"application/vnd.jupyter.widget-view+json": {
"model_id": "29f64ef5153445daad7e300c3c91e7f1",
"version_major": 2,
"version_minor": 0
},
"text/plain": [
"VBox(children=(Dropdown(description='Length:', layout=Layout(width='500px'), options=('Show All', '0.20 μm', '…"
]
},
"metadata": {},
"output_type": "display_data"
}
],
"source": [
"width_values = nmos.extracted_table['width']\n",
"id_values = nmos.extracted_table['id']\n",
@ -287,10 +302,25 @@
},
{
"cell_type": "code",
"execution_count": null,
"execution_count": 14,
"id": "3727c42d-a4bf-4eb0-bc11-6e859ae41324",
"metadata": {},
"outputs": [],
"outputs": [
{
"data": {
"application/vnd.jupyter.widget-view+json": {
"model_id": "9d62db56b7f240f9bd379086729554c4",
"version_major": 2,
"version_minor": 0
},
"text/plain": [
"VBox(children=(Dropdown(description='Length:', layout=Layout(width='500px'), options=('Show All', '0.20 μm', '…"
]
},
"metadata": {},
"output_type": "display_data"
}
],
"source": [
"width_values = pmos.extracted_table['width']\n",
"id_values = pmos.extracted_table['id']\n",

BIN
modules/module_1_bandgap_reference/part_3_layout/BGR_layout/final_bandgapreference/full_bandgap_layout_filled.gds
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Binary file not shown.

16
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid_extracted.cir
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@ -1,15 +1,15 @@
* Extracted by KLayout with SG13G2 LVS runset on : 27/03/2025 15:48
* Extracted by KLayout with SG13G2 LVS runset on : 07/04/2025 14:47
.SUBCKT input_common_centroid vdd dn3 v+ dn4 v\x2d
M$1 vdd vdd \$9 \$2 sg13_lv_pmos L=3.7u W=14.56u AS=4.9504p AD=4.9504p
.SUBCKT input_common_centroid vdd dn3 dn4 v\x2d v+
M$1 vdd vdd \$4 \$2 sg13_lv_pmos L=3.7u W=14.56u AS=4.9504p AD=4.9504p
+ PS=31.84u PD=31.84u
M$3 \$9 v+ dn4 \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PD=15.92u
M$4 \$9 v\x2d dn3 \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
M$2 \$4 v\x2d dn3 \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
+ PS=15.92u PD=15.92u
M$5 dn4 vdd vdd \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
M$3 dn3 vdd vdd \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PD=15.92u
M$6 dn3 vdd vdd \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
M$5 \$4 v+ dn4 \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PD=15.92u
M$6 dn4 vdd vdd \$2 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PD=15.92u
R$13 \$2 vdd ntap1 A=28.7556p P=185.52u
.ENDS input_common_centroid

53
modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sch
View File

@ -1,5 +1,4 @@
v {xschem version=3.4.5 file_version=1.2
}
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
@ -155,39 +154,39 @@ C {lab_pin.sym} 650 -570 3 0 {name=p9 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 700 -740 2 0 {name=p10 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -740 0 0 {name=M13
l=0.300u
w=10u
ng=1
w=18u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 630 -830 0 0 {name=M3
l=0.300u
w=10u
ng=1
l=0.3u
w=18u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 470 -570 0 0 {name=M2
l=0.200u
w=5u
ng=1
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -570 0 1 {name=M1
l=0.200u
w=5u
ng=1
l=200n
w=32u
ng=4
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1040 -530 0 0 {name=M4
l=0.200u
w=1u
w=8u
ng=1
m=1
model=sg13_lv_pmos
@ -195,55 +194,55 @@ spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 260 -530 0 1 {name=M5
l=0.200u
w=1u
w=8u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 260 -420 2 0 {name=M11
l=0.75u
w=1.0u
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 1040 -420 2 1 {name=M12
l=0.75u
w=1.0u
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 600 -200 2 0 {name=M6
l=0.75u
w=1.0u
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 380 -200 2 1 {name=M10
l=0.75u
w=1.0u
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 920 -200 2 0 {name=M7
l=0.75u
w=1.0u
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 700 -200 2 1 {name=M8
l=0.75u
w=1.0u
l=0.200u
w=4.0u
ng=1
m=1
model=sg13_lv_nmos

104
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/python/generate_sym.py
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@ -1,104 +0,0 @@
import re
import sys
import os
def parse_verilog(verilog_file):
"""Extract module name, inputs, and outputs from a Verilog file while expanding bus signals."""
with open(verilog_file, "r") as f:
code = f.read()
module_match = re.search(r"module\s+(\w+)\s*\(", code)
if not module_match:
raise ValueError("No module found in the Verilog file.")
module_name = module_match.group(1)
# Remove comments
code = re.sub(r"//.*", "", code)
# Adjusted regex to capture bus definitions properly
ports = re.findall(r"(input|output)\s*(?:wire|reg)?\s*(\[\d+:\d+\])?\s*(\w+)", code)
inputs = []
outputs = []
for direction, bus, name in ports:
if bus:
# Extract bus range
msb, lsb = map(int, re.findall(r"\d+", bus))
indices = range(msb, lsb - 1, -1) if msb >= lsb else range(msb, lsb + 1)
expanded_names = [f"{name}_{i}" for i in indices]
else:
expanded_names = [name]
if direction == "input":
inputs.extend(expanded_names)
else:
outputs.extend(expanded_names)
return module_name, inputs, outputs
def generate_xschem_symbol(verilog_file, output_sym):
"""Generate an Xschem symbol (.sym) for the given Verilog module with expanded bus signals."""
module_name, inputs, outputs = parse_verilog(verilog_file)
symbol = [
f'G {{}}',
f'K {{type=delay',
f'verilog_ignore=true',
f'vhdl_ignore=true',
f'format="@name [ {" ".join(f"@@{{{p}}}" for p in inputs)} ] [ {" ".join(f"@@{{{p}}}" for p in outputs)} ] null @dut"',
f'.model @dut @d_cosim_model simulation=@model',
f'template="name=adut',
f'dut=dut',
f'd_cosim_model=d_cosim',
f'model=./{os.path.basename(verilog_file)[:-2]}.so" }}',
f'V {{}}', f'S {{}}', f'E {{}}'
]
pin_distance, width, offset_factor = 20, 100, 30
total_pins = len(inputs) + len(outputs)
height_input_side = len(inputs) * pin_distance
height_output_side = len(outputs) * pin_distance
total_height = max(height_input_side, height_output_side)
start_y_input = -height_input_side // 2 + pin_distance // 2
start_y_output = -height_output_side // 2 + pin_distance // 2
for i, pin_name in enumerate(inputs):
y = start_y_input + pin_distance * i
symbol.append(f"B 5 -{width//2 + 2.5 + offset_factor} {y-2.5} -{width//2 - 2.5 + offset_factor} {y+2.5} {{name={pin_name} dir=in verilog_type=wire}}")
symbol.append(f"T {{{pin_name}}} -90 {y-2.5} 0 1 0.12 0.12 {{}}")
symbol.append(f"L 4 -{width // 2 + offset_factor} {y} -{width // 2} {y} {{}}")
for i, pin_name in enumerate(outputs):
y = start_y_output + pin_distance * i
symbol.append(f"B 5 {width//2 - 2.5 + offset_factor} {y-2.5} {width//2 + 2.5 + offset_factor} {y+2.5} {{name={pin_name} dir=out verilog_type=wire}}")
symbol.append(f"T {{{pin_name}}} 90 {y-2.5} 0 0 0.12 0.12 {{}}")
symbol.append(f"L 4 {width // 2 + offset_factor} {y} {width // 2} {y} {{}}")
symbol.append(f'L 4 {width//2} -{total_height//2} {width//2} {total_height//2} {{}}')
symbol.append(f'L 4 -{width//2} -{total_height//2} -{width//2} {total_height//2} {{}}')
symbol.append(f'L 4 -{width//2} {total_height//2} {width//2} {total_height//2} {{}}')
symbol.append(f'L 4 -{width//2} -{total_height//2} {width//2} -{total_height//2} {{}}')
symbol.append(f'T {{{module_name}}} 0 {total_height//2 + 5} 0 0 0.12 0.12 {{}}')
with open(output_sym, "w") as f:
f.write("\n".join(symbol))
print(f"Xschem symbol written to {output_sym}")
def main():
"""Main function to process Verilog and generate the symbol."""
if len(sys.argv) != 3:
print("\nUsage: python generate_sym.py <verilog_file> <symbol_file>")
print("Example: python generate_sym.py control.v test.sym\n")
sys.exit(1)
verilog_file, sym_file = sys.argv[1:3]
try:
module_name, inputs, outputs = parse_verilog(verilog_file)
print(f"Parsed module: {module_name}\nInputs: {inputs}\nOutputs: {outputs}")
generate_xschem_symbol(verilog_file, sym_file)
except Exception as e:
print(f"Error: {e}")
sys.exit(1)
if __name__ == "__main__":
main()

195
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo.out
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@ -1,195 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x590dd05c7420 .scope module, "sar_algorithm_tb" "sar_algorithm_tb" 2 3;
.timescale -9 -12;
v0x590dd05dff90_0 .net "B", 7 0, v0x590dd058b7b0_0; 1 drivers
v0x590dd05e0070_0 .net "BN", 7 0, v0x590dd058bba0_0; 1 drivers
v0x590dd05e0140_0 .net "D", 7 0, v0x590dd05df8e0_0; 1 drivers
v0x590dd05e0240_0 .var "En", 0 0;
v0x590dd05e0310_0 .var "Om", 0 0;
v0x590dd05e03b0_0 .var "Op", 0 0;
v0x590dd05e0480_0 .var "clk", 0 0;
v0x590dd05e0550_0 .var "rst", 0 0;
S_0x590dd05c75b0 .scope module, "uut" "sar_algorithm" 2 9, 3 3 0, S_0x590dd05c7420;
.timescale 0 0;
.port_info 0 /INPUT 1 "Op";
.port_info 1 /INPUT 1 "En";
.port_info 2 /INPUT 1 "Om";
.port_info 3 /INPUT 1 "clk";
.port_info 4 /INPUT 1 "rst";
.port_info 5 /OUTPUT 8 "B";
.port_info 6 /OUTPUT 8 "BN";
.port_info 7 /OUTPUT 8 "D";
v0x590dd058b7b0_0 .var "B", 7 0;
v0x590dd058bba0_0 .var "BN", 7 0;
v0x590dd05df8e0_0 .var "D", 7 0;
v0x590dd05df9a0_0 .net "En", 0 0, v0x590dd05e0240_0; 1 drivers
v0x590dd05dfa60_0 .net "Om", 0 0, v0x590dd05e0310_0; 1 drivers
v0x590dd05dfb70_0 .net "Op", 0 0, v0x590dd05e03b0_0; 1 drivers
v0x590dd05dfc30_0 .net "clk", 0 0, v0x590dd05e0480_0; 1 drivers
v0x590dd05dfcf0_0 .var "counter", 2 0;
v0x590dd05dfdd0_0 .net "rst", 0 0, v0x590dd05e0550_0; 1 drivers
E_0x590dd05c3e10 .event posedge, v0x590dd05dfc30_0;
.scope S_0x590dd05c75b0;
T_0 ;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x590dd05dfcf0_0, 0, 3;
%end;
.thread T_0;
.scope S_0x590dd05c75b0;
T_1 ;
%wait E_0x590dd05c3e10;
%load/vec4 v0x590dd05df9a0_0;
%load/vec4 v0x590dd05dfdd0_0;
%nor/r;
%and;
%load/vec4 v0x590dd05dfb70_0;
%load/vec4 v0x590dd05dfa60_0;
%xor;
%and;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0x590dd05dfcf0_0;
%cmpi/ne 7, 0, 3;
%jmp/0xz T_1.2, 4;
%load/vec4 v0x590dd05dfb70_0;
%ix/load 5, 0, 0;
%ix/getv 4, v0x590dd05dfcf0_0;
%assign/vec4/off/d v0x590dd05df8e0_0, 4, 5;
%load/vec4 v0x590dd05dfb70_0;
%flag_set/vec4 8;
%jmp/0xz T_1.4, 8;
%pushi/vec4 1, 0, 1;
%ix/load 5, 0, 0;
%ix/getv 4, v0x590dd05dfcf0_0;
%assign/vec4/off/d v0x590dd058b7b0_0, 4, 5;
%pushi/vec4 0, 0, 1;
%ix/load 5, 0, 0;
%ix/getv 4, v0x590dd05dfcf0_0;
%assign/vec4/off/d v0x590dd058bba0_0, 4, 5;
%jmp T_1.5;
T_1.4 ;
%load/vec4 v0x590dd05dfa60_0;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%pushi/vec4 0, 0, 1;
%ix/load 5, 0, 0;
%ix/getv 4, v0x590dd05dfcf0_0;
%assign/vec4/off/d v0x590dd058b7b0_0, 4, 5;
%pushi/vec4 1, 0, 1;
%ix/load 5, 0, 0;
%ix/getv 4, v0x590dd05dfcf0_0;
%assign/vec4/off/d v0x590dd058bba0_0, 4, 5;
T_1.6 ;
T_1.5 ;
%load/vec4 v0x590dd05dfcf0_0;
%addi 1, 0, 3;
%assign/vec4 v0x590dd05dfcf0_0, 0;
T_1.2 ;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0x590dd05dfdd0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.8, 8;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0x590dd058b7b0_0, 0;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0x590dd058bba0_0, 0;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0x590dd05df8e0_0, 0;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0x590dd05dfcf0_0, 0;
T_1.8 ;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_0x590dd05c7420;
T_2 ;
%delay 10000, 0;
%load/vec4 v0x590dd05e0480_0;
%inv;
%store/vec4 v0x590dd05e0480_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_0x590dd05c7420;
T_3 ;
%vpi_call 2 24 "$dumpfile", "sar_algo_tb.vcd" {0 0 0};
%vpi_call 2 25 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x590dd05c7420 {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0480_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0550_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0240_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e0550_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0550_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e0240_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e03b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x590dd05e0310_0, 0, 1;
%delay 10000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x590dd05e0550_0, 0, 1;
%delay 50000, 0;
%vpi_call 2 51 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"sar_algo_tb.v";
"sar_algo.v";

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//Verilog HDL for "8_bit_SAR_ADC", "sar_algorithm" "functional"
module sar_algorithm (
input wire Op,
input wire En,
input wire Om,
input wire clk,
input wire rst,
output reg [7:0] B, // 8-bit
output reg [7:0] BN, // 8-bit
output reg [7:0] D // 8-bit
);
reg [2:0] counter = 3'b000; // 3-bit counter
always @(posedge clk) begin
if (En && !rst && (Op ^ Om)) begin
if (counter != 3'b111) begin // Limit to 8
D[counter] <= Op;
if (Op) begin
B[counter] <= 1'b1;
BN[counter] <= 1'b0;
end else if (Om) begin
B[counter] <= 1'b0;
BN[counter] <= 1'b1;
end
counter <= counter + 1'b1;
end
end else if (rst) begin
B <= 8'b00000000;
BN <= 8'b00000000;
D <= 8'b00000000;
counter <= 3'b000;
end
end
endmodule

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts)
#include "Vlng__pch.h"
//============================================================
// Constructors
Vlng::Vlng(VerilatedContext* _vcontextp__, const char* _vcname__)
: VerilatedModel{*_vcontextp__}
, vlSymsp{new Vlng__Syms(contextp(), _vcname__, this)}
, clk{vlSymsp->TOP.clk}
, Op{vlSymsp->TOP.Op}
, En{vlSymsp->TOP.En}
, Om{vlSymsp->TOP.Om}
, rst{vlSymsp->TOP.rst}
, B{vlSymsp->TOP.B}
, BN{vlSymsp->TOP.BN}
, D{vlSymsp->TOP.D}
, rootp{&(vlSymsp->TOP)}
{
// Register model with the context
contextp()->addModel(this);
}
Vlng::Vlng(const char* _vcname__)
: Vlng(Verilated::threadContextp(), _vcname__)
{
}
//============================================================
// Destructor
Vlng::~Vlng() {
delete vlSymsp;
}
//============================================================
// Evaluation function
#ifdef VL_DEBUG
void Vlng___024root___eval_debug_assertions(Vlng___024root* vlSelf);
#endif // VL_DEBUG
void Vlng___024root___eval_static(Vlng___024root* vlSelf);
void Vlng___024root___eval_initial(Vlng___024root* vlSelf);
void Vlng___024root___eval_settle(Vlng___024root* vlSelf);
void Vlng___024root___eval(Vlng___024root* vlSelf);
void Vlng::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vlng::eval_step\n"); );
#ifdef VL_DEBUG
// Debug assertions
Vlng___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif // VL_DEBUG
vlSymsp->__Vm_deleter.deleteAll();
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
vlSymsp->__Vm_didInit = true;
VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
Vlng___024root___eval_static(&(vlSymsp->TOP));
Vlng___024root___eval_initial(&(vlSymsp->TOP));
Vlng___024root___eval_settle(&(vlSymsp->TOP));
}
VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
Vlng___024root___eval(&(vlSymsp->TOP));
// Evaluate cleanup
Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
}
//============================================================
// Events and timing
bool Vlng::eventsPending() { return false; }
uint64_t Vlng::nextTimeSlot() {
VL_FATAL_MT(__FILE__, __LINE__, "", "No delays in the design");
return 0;
}
//============================================================
// Utilities
const char* Vlng::name() const {
return vlSymsp->name();
}
//============================================================
// Invoke final blocks
void Vlng___024root___eval_final(Vlng___024root* vlSelf);
VL_ATTR_COLD void Vlng::final() {
Vlng___024root___eval_final(&(vlSymsp->TOP));
}
//============================================================
// Implementations of abstract methods from VerilatedModel
const char* Vlng::hierName() const { return vlSymsp->name(); }
const char* Vlng::modelName() const { return "Vlng"; }
unsigned Vlng::threads() const { return 1; }
void Vlng::prepareClone() const { contextp()->prepareClone(); }
void Vlng::atClone() const {
contextp()->threadPoolpOnClone();
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary model header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef VERILATED_VLNG_H_
#define VERILATED_VLNG_H_ // guard
#include "verilated.h"
class Vlng__Syms;
class Vlng___024root;
// This class is the main interface to the Verilated model
class alignas(VL_CACHE_LINE_BYTES) Vlng VL_NOT_FINAL : public VerilatedModel {
private:
// Symbol table holding complete model state (owned by this class)
Vlng__Syms* const vlSymsp;
public:
// CONSTEXPR CAPABILITIES
// Verilated with --trace?
static constexpr bool traceCapable = false;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(&clk,0,0);
VL_IN8(&Op,0,0);
VL_IN8(&En,0,0);
VL_IN8(&Om,0,0);
VL_IN8(&rst,0,0);
VL_OUT8(&B,7,0);
VL_OUT8(&BN,7,0);
VL_OUT8(&D,7,0);
// CELLS
// Public to allow access to /* verilator public */ items.
// Otherwise the application code can consider these internals.
// Root instance pointer to allow access to model internals,
// including inlined /* verilator public_flat_* */ items.
Vlng___024root* const rootp;
// CONSTRUCTORS
/// Construct the model; called by application code
/// If contextp is null, then the model will use the default global context
/// If name is "", then makes a wrapper with a
/// single model invisible with respect to DPI scope names.
explicit Vlng(VerilatedContext* contextp, const char* name = "TOP");
explicit Vlng(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
virtual ~Vlng();
private:
VL_UNCOPYABLE(Vlng); ///< Copying not allowed
public:
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step.
void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes.
void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion.
void final();
/// Are there scheduled events to handle?
bool eventsPending();
/// Returns time at next time slot. Aborts if !eventsPending()
uint64_t nextTimeSlot();
/// Trace signals in the model; called by application code
void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) { contextp()->trace(tfp, levels, options); }
/// Retrieve name of this model instance (as passed to constructor).
const char* name() const;
// Abstract methods from VerilatedModel
const char* hierName() const override final;
const char* modelName() const override final;
unsigned threads() const override final;
/// Prepare for cloning the model at the process level (e.g. fork in Linux)
/// Release necessary resources. Called before cloning.
void prepareClone() const;
/// Re-init after cloning the model at the process level (e.g. fork in Linux)
/// Re-allocate necessary resources. Called after cloning.
void atClone() const;
private:
// Internal functions - trace registration
void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);
};
#endif // guard

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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vlng.mk
default: Vlng
### Constants...
# Perl executable (from $PERL, defaults to 'perl' if not set)
PERL = perl
# Python3 executable (from $PYTHON3, defaults to 'python3' if not set)
PYTHON3 = python3
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# C++ code coverage 0/1 (from --prof-c)
VM_PROFC = 0
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vlng
# Module prefix (from --prefix)
VM_MODPREFIX = Vlng
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-I/usr/local/share/ngspice/scripts/src \
-fpic \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
verilator_main \
verilator_shim \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
.. \
../../../../../../../../../usr/local/share/ngspice/scripts/src \
### Default rules...
# Include list of all generated classes
include Vlng_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vlng: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
# Verilated -*- Makefile -*-

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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vlng.cpp"
#include "Vlng___024root__DepSet_h9def6047__0.cpp"
#include "Vlng___024root__DepSet_h26a4896e__0.cpp"
#include "Vlng___024root__Slow.cpp"
#include "Vlng___024root__DepSet_h26a4896e__0__Slow.cpp"
#include "Vlng__Syms.cpp"

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Vlng__ALL.o: Vlng__ALL.cpp Vlng.cpp Vlng__pch.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_config.h \
/usr/local/share/verilator/include/verilated_types.h \
/usr/local/share/verilator/include/verilated_funcs.h Vlng__Syms.h Vlng.h \
Vlng___024root.h Vlng___024root__DepSet_h9def6047__0.cpp \
Vlng___024root__DepSet_h26a4896e__0.cpp Vlng___024root__Slow.cpp \
Vlng___024root__DepSet_h26a4896e__0__Slow.cpp Vlng__Syms.cpp

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vlng__pch.h"
#include "Vlng.h"
#include "Vlng___024root.h"
// FUNCTIONS
Vlng__Syms::~Vlng__Syms()
{
}
Vlng__Syms::Vlng__Syms(VerilatedContext* contextp, const char* namep, Vlng* modelp)
: VerilatedSyms{contextp}
// Setup internal state of the Syms class
, __Vm_modelp{modelp}
// Setup module instances
, TOP{this, namep}
{
// Check resources
Verilated::stackCheck(11);
// Configure time unit / time precision
_vm_contextp__->timeunit(-12);
_vm_contextp__->timeprecision(-12);
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOP.__Vconfigure(true);
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef VERILATED_VLNG__SYMS_H_
#define VERILATED_VLNG__SYMS_H_ // guard
#include "verilated.h"
// INCLUDE MODEL CLASS
#include "Vlng.h"
// INCLUDE MODULE CLASSES
#include "Vlng___024root.h"
// SYMS CLASS (contains all model state)
class alignas(VL_CACHE_LINE_BYTES)Vlng__Syms final : public VerilatedSyms {
public:
// INTERNAL STATE
Vlng* const __Vm_modelp;
VlDeleter __Vm_deleter;
bool __Vm_didInit = false;
// MODULE INSTANCE STATE
Vlng___024root TOP;
// CONSTRUCTORS
Vlng__Syms(VerilatedContext* contextp, const char* namep, Vlng* modelp);
~Vlng__Syms();
// METHODS
const char* name() { return TOP.name(); }
};
#endif // guard

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vlng.h for the primary calling header
#ifndef VERILATED_VLNG___024ROOT_H_
#define VERILATED_VLNG___024ROOT_H_ // guard
#include "verilated.h"
class Vlng__Syms;
class alignas(VL_CACHE_LINE_BYTES) Vlng___024root final : public VerilatedModule {
public:
// DESIGN SPECIFIC STATE
VL_IN8(clk,0,0);
VL_IN8(Op,0,0);
VL_IN8(En,0,0);
VL_IN8(Om,0,0);
VL_IN8(rst,0,0);
VL_OUT8(B,7,0);
VL_OUT8(BN,7,0);
VL_OUT8(D,7,0);
CData/*2:0*/ sar_algorithm__DOT__counter;
CData/*0:0*/ __Vtrigprevexpr___TOP__clk__0;
CData/*0:0*/ __VactContinue;
IData/*31:0*/ __VactIterCount;
VlTriggerVec<1> __VactTriggered;
VlTriggerVec<1> __VnbaTriggered;
// INTERNAL VARIABLES
Vlng__Syms* const vlSymsp;
// CONSTRUCTORS
Vlng___024root(Vlng__Syms* symsp, const char* v__name);
~Vlng___024root();
VL_UNCOPYABLE(Vlng___024root);
// INTERNAL METHODS
void __Vconfigure(bool first);
};
#endif // guard

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng__pch.h"
#include "Vlng___024root.h"
void Vlng___024root___eval_act(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_act\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
}
void Vlng___024root___nba_sequent__TOP__0(Vlng___024root* vlSelf);
void Vlng___024root___eval_nba(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_nba\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
if ((1ULL & vlSelfRef.__VnbaTriggered.word(0U))) {
Vlng___024root___nba_sequent__TOP__0(vlSelf);
}
}
VL_INLINE_OPT void Vlng___024root___nba_sequent__TOP__0(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___nba_sequent__TOP__0\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
if ((((IData)(vlSelfRef.En) & (~ (IData)(vlSelfRef.rst)))
& ((IData)(vlSelfRef.Op) ^ (IData)(vlSelfRef.Om)))) {
if ((7U != (IData)(vlSelfRef.sar_algorithm__DOT__counter))) {
vlSelfRef.D = (((~ ((IData)(1U) << (IData)(vlSelfRef.sar_algorithm__DOT__counter)))
& (IData)(vlSelfRef.D))
| (0xffU & ((IData)(vlSelfRef.Op)
<< (IData)(vlSelfRef.sar_algorithm__DOT__counter))));
if (vlSelfRef.Op) {
vlSelfRef.B = ((IData)(vlSelfRef.B)
| (0xffU & ((IData)(1U)
<< (IData)(vlSelfRef.sar_algorithm__DOT__counter))));
vlSelfRef.BN = ((~ ((IData)(1U) << (IData)(vlSelfRef.sar_algorithm__DOT__counter)))
& (IData)(vlSelfRef.BN));
} else if (vlSelfRef.Om) {
vlSelfRef.B = ((~ ((IData)(1U) << (IData)(vlSelfRef.sar_algorithm__DOT__counter)))
& (IData)(vlSelfRef.B));
vlSelfRef.BN = ((IData)(vlSelfRef.BN)
| (0xffU & ((IData)(1U)
<< (IData)(vlSelfRef.sar_algorithm__DOT__counter))));
}
vlSelfRef.sar_algorithm__DOT__counter =
(7U & ((IData)(1U) + (IData)(vlSelfRef.sar_algorithm__DOT__counter)));
}
} else if (vlSelfRef.rst) {
vlSelfRef.sar_algorithm__DOT__counter = 0U;
vlSelfRef.B = 0U;
vlSelfRef.BN = 0U;
vlSelfRef.D = 0U;
}
}
void Vlng___024root___eval_triggers__act(Vlng___024root* vlSelf);
bool Vlng___024root___eval_phase__act(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_phase__act\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Init
VlTriggerVec<1> __VpreTriggered;
CData/*0:0*/ __VactExecute;
// Body
Vlng___024root___eval_triggers__act(vlSelf);
__VactExecute = vlSelfRef.__VactTriggered.any();
if (__VactExecute) {
__VpreTriggered.andNot(vlSelfRef.__VactTriggered, vlSelfRef.__VnbaTriggered);
vlSelfRef.__VnbaTriggered.thisOr(vlSelfRef.__VactTriggered);
Vlng___024root___eval_act(vlSelf);
}
return (__VactExecute);
}
bool Vlng___024root___eval_phase__nba(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_phase__nba\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Init
CData/*0:0*/ __VnbaExecute;
// Body
__VnbaExecute = vlSelfRef.__VnbaTriggered.any();
if (__VnbaExecute) {
Vlng___024root___eval_nba(vlSelf);
vlSelfRef.__VnbaTriggered.clear();
}
return (__VnbaExecute);
}
#ifdef VL_DEBUG
VL_ATTR_COLD void Vlng___024root___dump_triggers__nba(Vlng___024root* vlSelf);
#endif // VL_DEBUG
#ifdef VL_DEBUG
VL_ATTR_COLD void Vlng___024root___dump_triggers__act(Vlng___024root* vlSelf);
#endif // VL_DEBUG
void Vlng___024root___eval(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Init
IData/*31:0*/ __VnbaIterCount;
CData/*0:0*/ __VnbaContinue;
// Body
__VnbaIterCount = 0U;
__VnbaContinue = 1U;
while (__VnbaContinue) {
if (VL_UNLIKELY(((0x64U < __VnbaIterCount)))) {
#ifdef VL_DEBUG
Vlng___024root___dump_triggers__nba(vlSelf);
#endif
VL_FATAL_MT("sar_algo.v", 3, "", "NBA region did not converge.");
}
__VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
__VnbaContinue = 0U;
vlSelfRef.__VactIterCount = 0U;
vlSelfRef.__VactContinue = 1U;
while (vlSelfRef.__VactContinue) {
if (VL_UNLIKELY(((0x64U < vlSelfRef.__VactIterCount)))) {
#ifdef VL_DEBUG
Vlng___024root___dump_triggers__act(vlSelf);
#endif
VL_FATAL_MT("sar_algo.v", 3, "", "Active region did not converge.");
}
vlSelfRef.__VactIterCount = ((IData)(1U)
+ vlSelfRef.__VactIterCount);
vlSelfRef.__VactContinue = 0U;
if (Vlng___024root___eval_phase__act(vlSelf)) {
vlSelfRef.__VactContinue = 1U;
}
}
if (Vlng___024root___eval_phase__nba(vlSelf)) {
__VnbaContinue = 1U;
}
}
}
#ifdef VL_DEBUG
void Vlng___024root___eval_debug_assertions(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_debug_assertions\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
if (VL_UNLIKELY(((vlSelfRef.Op & 0xfeU)))) {
Verilated::overWidthError("Op");}
if (VL_UNLIKELY(((vlSelfRef.En & 0xfeU)))) {
Verilated::overWidthError("En");}
if (VL_UNLIKELY(((vlSelfRef.Om & 0xfeU)))) {
Verilated::overWidthError("Om");}
if (VL_UNLIKELY(((vlSelfRef.clk & 0xfeU)))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY(((vlSelfRef.rst & 0xfeU)))) {
Verilated::overWidthError("rst");}
}
#endif // VL_DEBUG

91
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/Vlng___024root__DepSet_h26a4896e__0__Slow.cpp
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@ -1,91 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng__pch.h"
#include "Vlng___024root.h"
VL_ATTR_COLD void Vlng___024root___eval_static__TOP(Vlng___024root* vlSelf);
VL_ATTR_COLD void Vlng___024root___eval_static(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_static\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
Vlng___024root___eval_static__TOP(vlSelf);
}
VL_ATTR_COLD void Vlng___024root___eval_static__TOP(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_static__TOP\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
vlSelfRef.sar_algorithm__DOT__counter = 0U;
}
VL_ATTR_COLD void Vlng___024root___eval_initial(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_initial\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
vlSelfRef.__Vtrigprevexpr___TOP__clk__0 = vlSelfRef.clk;
}
VL_ATTR_COLD void Vlng___024root___eval_final(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_final\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
}
VL_ATTR_COLD void Vlng___024root___eval_settle(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_settle\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
}
#ifdef VL_DEBUG
VL_ATTR_COLD void Vlng___024root___dump_triggers__act(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___dump_triggers__act\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
if ((1U & (~ vlSelfRef.__VactTriggered.any()))) {
VL_DBG_MSGF(" No triggers active\n");
}
if ((1ULL & vlSelfRef.__VactTriggered.word(0U))) {
VL_DBG_MSGF(" 'act' region trigger index 0 is active: @(posedge clk)\n");
}
}
#endif // VL_DEBUG
#ifdef VL_DEBUG
VL_ATTR_COLD void Vlng___024root___dump_triggers__nba(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___dump_triggers__nba\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
if ((1U & (~ vlSelfRef.__VnbaTriggered.any()))) {
VL_DBG_MSGF(" No triggers active\n");
}
if ((1ULL & vlSelfRef.__VnbaTriggered.word(0U))) {
VL_DBG_MSGF(" 'nba' region trigger index 0 is active: @(posedge clk)\n");
}
}
#endif // VL_DEBUG
VL_ATTR_COLD void Vlng___024root___ctor_var_reset(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___ctor_var_reset\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
vlSelf->Op = VL_RAND_RESET_I(1);
vlSelf->En = VL_RAND_RESET_I(1);
vlSelf->Om = VL_RAND_RESET_I(1);
vlSelf->clk = VL_RAND_RESET_I(1);
vlSelf->rst = VL_RAND_RESET_I(1);
vlSelf->B = VL_RAND_RESET_I(8);
vlSelf->BN = VL_RAND_RESET_I(8);
vlSelf->D = VL_RAND_RESET_I(8);
vlSelf->sar_algorithm__DOT__counter = VL_RAND_RESET_I(3);
vlSelf->__Vtrigprevexpr___TOP__clk__0 = VL_RAND_RESET_I(1);
}

26
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/Vlng___024root__DepSet_h9def6047__0.cpp
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@ -1,26 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng__pch.h"
#include "Vlng__Syms.h"
#include "Vlng___024root.h"
#ifdef VL_DEBUG
VL_ATTR_COLD void Vlng___024root___dump_triggers__act(Vlng___024root* vlSelf);
#endif // VL_DEBUG
void Vlng___024root___eval_triggers__act(Vlng___024root* vlSelf) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vlng___024root___eval_triggers__act\n"); );
Vlng__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
auto& vlSelfRef = std::ref(*vlSelf).get();
// Body
vlSelfRef.__VactTriggered.set(0U, ((IData)(vlSelfRef.clk)
& (~ (IData)(vlSelfRef.__Vtrigprevexpr___TOP__clk__0))));
vlSelfRef.__Vtrigprevexpr___TOP__clk__0 = vlSelfRef.clk;
#ifdef VL_DEBUG
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
Vlng___024root___dump_triggers__act(vlSelf);
}
#endif
}

24
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/Vlng___024root__Slow.cpp
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@ -1,24 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vlng.h for the primary calling header
#include "Vlng__pch.h"
#include "Vlng__Syms.h"
#include "Vlng___024root.h"
void Vlng___024root___ctor_var_reset(Vlng___024root* vlSelf);
Vlng___024root::Vlng___024root(Vlng__Syms* symsp, const char* v__name)
: VerilatedModule{v__name}
, vlSymsp{symsp}
{
// Reset structure values
Vlng___024root___ctor_var_reset(this);
}
void Vlng___024root::__Vconfigure(bool first) {
(void)first; // Prevent unused variable warning
}
Vlng___024root::~Vlng___024root() {
}

28
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/Vlng__pch.h
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@ -1,28 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Precompiled header
//
// Internal details; most user sources do not need this header,
// unless using verilator public meta comments.
// Suggest use Vlng.h instead.
#ifndef VERILATED_VLNG__PCH_H_
#define VERILATED_VLNG__PCH_H_ // guard
// GCC and Clang only will precompile headers (PCH) for the first header.
// So, make sure this is the one and only PCH.
// If multiple module's includes are needed, use individual includes.
#ifdef VL_PCH_INCLUDED
# error "Including multiple precompiled header files"
#endif
#define VL_PCH_INCLUDED
#include "verilated.h"
#include "Vlng__Syms.h"
#include "Vlng.h"
// Additional include files added using '--compiler-include'
#endif // guard

1
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/Vlng__ver.d
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@ -1 +0,0 @@
sar_algo_obj_dir/Vlng.cpp sar_algo_obj_dir/Vlng.h sar_algo_obj_dir/Vlng.mk sar_algo_obj_dir/Vlng__Syms.cpp sar_algo_obj_dir/Vlng__Syms.h sar_algo_obj_dir/Vlng___024root.h sar_algo_obj_dir/Vlng___024root__DepSet_h26a4896e__0.cpp sar_algo_obj_dir/Vlng___024root__DepSet_h26a4896e__0__Slow.cpp sar_algo_obj_dir/Vlng___024root__DepSet_h9def6047__0.cpp sar_algo_obj_dir/Vlng___024root__Slow.cpp sar_algo_obj_dir/Vlng__pch.h sar_algo_obj_dir/Vlng__ver.d sar_algo_obj_dir/Vlng_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin /usr/local/share/verilator/include/verilated_std.sv /usr/local/share/verilator/include/verilated_std_waiver.vlt sar_algo.v

51
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/Vlng_classes.mk
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@ -1,51 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vlng.mk for the caller.
### Switches...
# C11 constructs required? 0/1 (always on now)
VM_C11 = 1
# Timing enabled? 0/1
VM_TIMING = 0
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Parallel builds? 0/1 (from --output-split)
VM_PARALLEL_BUILDS = 0
# Tracing output mode? 0/1 (from --trace/--trace-fst)
VM_TRACE = 0
# Tracing output mode in VCD format? 0/1 (from --trace)
VM_TRACE_VCD = 0
# Tracing output mode in FST format? 0/1 (from --trace-fst)
VM_TRACE_FST = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vlng \
Vlng___024root__DepSet_h9def6047__0 \
Vlng___024root__DepSet_h26a4896e__0 \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
Vlng___024root__Slow \
Vlng___024root__DepSet_h26a4896e__0__Slow \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vlng__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_threads \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

1
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/inouts.h
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@ -1 +0,0 @@
/* Generated code: do not edit. */

6
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/inputs.h
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@ -1,6 +0,0 @@
/* Generated code: do not edit. */
VL_DATA(8,clk,0,0)
VL_DATA(8,Op,0,0)
VL_DATA(8,En,0,0)
VL_DATA(8,Om,0,0)
VL_DATA(8,rst,0,0)

4
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/outputs.h
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@ -1,4 +0,0 @@
/* Generated code: do not edit. */
VL_DATA(8,B,7,0)
VL_DATA(8,BN,7,0)
VL_DATA(8,D,7,0)

12
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/verilated.d
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@ -1,12 +0,0 @@
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilated_config.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_types.h \
/usr/local/share/verilator/include/verilated_funcs.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_threads.h \
/usr/local/share/verilator/include/verilated_trace.h \
/usr/local/share/verilator/include/verilatedos_c.h

BIN
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/verilated.o
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8
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/verilated_threads.d
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@ -1,8 +0,0 @@
verilated_threads.o: \
/usr/local/share/verilator/include/verilated_threads.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_threads.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_config.h \
/usr/local/share/verilator/include/verilated_types.h \
/usr/local/share/verilator/include/verilated_funcs.h

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4
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/verilator_main.d
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@ -1,4 +0,0 @@
verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp \
/usr/local/share/ngspice/scripts/src/ngspice/cmtypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/miftypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/cosim.h

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10
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_obj_dir/verilator_shim.d
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@ -1,10 +0,0 @@
verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_config.h \
/usr/local/share/verilator/include/verilated_types.h \
/usr/local/share/verilator/include/verilated_funcs.h Vlng.h \
/usr/local/share/ngspice/scripts/src/ngspice/cmtypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/miftypes.h \
/usr/local/share/ngspice/scripts/src/ngspice/cosim.h outputs.h inouts.h \
inputs.h

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54
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_tb.v
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@ -1,54 +0,0 @@
`timescale 1ns / 1ps
module sar_algorithm_tb();
reg Op, En, Om, clk, rst;
wire [7:0] B, BN, D;
// Instantiate the SAR algorithm module
sar_algorithm uut (
.Op(Op),
.En(En),
.Om(Om),
.clk(clk),
.rst(rst),
.B(B),
.BN(BN),
.D(D)
);
// Clock generation
always #10 clk = ~clk; // 10ns period (100 MHz)
initial begin
$dumpfile("sar_algo_tb.vcd");
$dumpvars(0, sar_algorithm_tb);
// Initialize signals
clk = 0;
rst = 0;
En = 0;
Op = 0;
Om = 0;
// Apply reset
#10 rst = 1;
#10 rst = 0; En = 1;
// Provide input pattern
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 Op = 1; Om = 0;
#10 rst = 1;
// End simulation
#50 $finish;
end
endmodule

114
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/sar_algo_tb.vcd
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@ -1,114 +0,0 @@
$date
Thu Mar 20 14:50:00 2025
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module sar_algorithm_tb $end
$var wire 8 ! D [7:0] $end
$var wire 8 " BN [7:0] $end
$var wire 8 # B [7:0] $end
$var reg 1 $ En $end
$var reg 1 % Om $end
$var reg 1 & Op $end
$var reg 1 ' clk $end
$var reg 1 ( rst $end
$scope module uut $end
$var wire 1 $ En $end
$var wire 1 % Om $end
$var wire 1 & Op $end
$var wire 1 ' clk $end
$var wire 1 ( rst $end
$var reg 8 ) B [7:0] $end
$var reg 8 * BN [7:0] $end
$var reg 8 + D [7:0] $end
$var reg 3 , counter [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 ,
bx +
bx *
bx )
0(
0'
0&
0%
0$
bx #
bx "
bx !
$end
#10000
b0 !
b0 +
b0 "
b0 *
b0 #
b0 )
1(
1'
#20000
1$
0(
0'
#30000
b1 ,
b1 #
b1 )
b1 !
b1 +
1&
1'
#40000
0'
#50000
b10 ,
b11 #
b11 )
b11 !
b11 +
1'
#60000
0'
#70000
b11 ,
b111 #
b111 )
b111 !
b111 +
1'
#80000
0'
#90000
b100 ,
b1111 #
b1111 )
b1111 !
b1111 +
1'
#100000
0'
#110000
b0 ,
b0 !
b0 +
b0 #
b0 )
1(
1'
#120000
0'
#130000
1'
#140000
0'
#150000
1'
#160000
0'

45
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/xschem/d_osc.sym
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@ -1,45 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name @@c2 @@c1 @clk
.model @clk @d_osc_model cntl_array=[-1 1] \
+ freq_array=[ @freq @freq ]"
template="name=aclock
clk=clk
d_osc_model=d_osc
freq=1Meg
"
}
V {}
S {}
E {}
L 4 20 -20 20 20 {}
L 4 -20 -20 -20 20 {}
L 4 -20 20 20 20 {}
L 4 -20 -20 20 -20 {}
B 5 -2.5 17.5 2.5 22.5 {name=c2 dir=out}
B 5 -2.5 -22.5 2.5 -17.5 {name=c1 dir=out}
T {@name} 25 -10 0 0 0.12 0.12 {}
T {@d_osc_model} 20 0 0 0 0.12 0.12 {}

127
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/xschem/sar_algo.sym
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@ -1,127 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@Op @@En @@Om @@clk @@rst ] [ @@B7 @@B6 @@B5 @@B4 @@B3 @@B2 @@B1 @@B0 @@BN7 @@BN6 @@BN5 @@BN4 @@BN3 @@BN2 @@BN1 @@BN0 @@D7 @@D6 @@D5 @@D4 @@D3 @@D2 @@D1 @@D0 ] null @dut
.model @dut @d_cosim_model simulation=@model"
template="name=adut
dut=dut
d_cosim_model=d_cosim
model=./sar_algo.so"
}
V {}
S {}
E {}
B 5 -82.5 -42.5 -77.5 -37.5 {name=Op dir=in verilog_type=wire propag=0}
T {Op} -90 -42.5 0 1 0.12 0.12 {}
L 4 -80 -40 -50 -40 {}
B 5 -82.5 -22.5 -77.5 -17.5 {name=En dir=in verilog_type=wire propag=0}
T {En} -90 -22.5 0 1 0.12 0.12 {}
L 4 -80 -20 -50 -20 {}
B 5 -82.5 -2.5 -77.5 2.5 {name=Om dir=in verilog_type=wire propag=0}
T {Om} -90 -2.5 0 1 0.12 0.12 {}
L 4 -80 0 -50 0 {}
B 5 -82.5 17.5 -77.5 22.5 {name=clk dir=in verilog_type=wire propag=0}
T {clk} -90 17.5 0 1 0.12 0.12 {}
L 4 -80 20 -50 20 {}
B 5 -82.5 37.5 -77.5 42.5 {name=rst dir=in verilog_type=wire propag=0}
T {rst} -90 37.5 0 1 0.12 0.12 {}
L 4 -80 40 -50 40 {}
B 5 77.5 -232.5 82.5 -227.5 {name=B7 dir=out verilog_type=wire propag=1}
T {B_7} 90 -232.5 0 0 0.12 0.12 {}
L 4 80 -230 50 -230 {}
B 5 77.5 -212.5 82.5 -207.5 {name=B6 dir=out verilog_type=wire propag=1}
T {B_6} 90 -212.5 0 0 0.12 0.12 {}
L 4 80 -210 50 -210 {}
B 5 77.5 -192.5 82.5 -187.5 {name=B5 dir=out verilog_type=wire propag=1}
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505
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/xschem/sar_algo.tb
View File

@ -1,505 +0,0 @@
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value="
.control
save all
tran 50n 6u
write sar_algo.raw
.endc
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}
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}
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}
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}
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}
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}
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BIN
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/xschem/simulations/sar_algo.so
View File

Binary file not shown.

42
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sch Normal file
View File

@ -0,0 +1,42 @@
v {xschem version=3.4.6 file_version=1.2}
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34
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym Normal file
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@ -0,0 +1,34 @@
v {xschem version=3.4.6 file_version=1.2}
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A 4 0 -37.5 7.071067811865476 45 360 {}
P 4 5 0 -30 -60 -60 -60 0 0 -30 0 -30 {}
P 4 5 0 -30 60 -60 60 0 0 -30 0 -30 {}
P 4 5 0 30 -60 0 -60 60 0 30 0 30 {}
P 4 5 0 30 60 0 60 60 0 30 0 30 {}
T {@symname} -59 14 0 0 0.3 0.3 {}
T {@name} 25 -72 0 0 0.2 0.2 {}
T {!Control} 22.5 -59 0 1 0.2 0.2 {}
T {Vin} -45 -6.5 0 0 0.2 0.2 {}
T {Vout} 52.5 -6.5 0 1 0.2 0.2 {}
T {gnd} -60 41 0 0 0.2 0.2 {}
T {Control} -15 54 2 1 0.2 0.2 {}
T {vdd} -60 -36 2 1 0.2 0.2 {}

144
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/testbench/T_gate_switch_tb.sch Normal file
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@ -0,0 +1,144 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 760 -750 1560 -350 {flags=graph
y1=0
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.0001
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=control
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
B 2 760 -1160 1560 -760 {flags=graph
y1=0.6
y2=0.62
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.0001
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
color=4
node=vref}
B 2 1590 -750 2390 -350 {flags=graph
y1=-0.0006
y2=0.61
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.0001
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vo
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
N 40 -630 40 -600 {lab=vref}
N 40 -540 40 -510 {lab=GND}
N 40 -480 40 -450 {lab=Control}
N 40 -390 40 -360 {lab=GND}
N 40 -780 40 -750 {lab=vdd}
N 40 -690 40 -660 {lab=GND}
N 400 -610 400 -580 {lab=Control}
N 480 -690 540 -690 {lab=Vo}
N 400 -940 400 -770 {lab=#net1}
N 480 -1020 540 -1020 {lab=Vo}
N 540 -860 540 -690 {lab=Vo}
N 570 -860 590 -860 {lab=Vo}
N 540 -1020 540 -860 {lab=Vo}
N 400 -1170 400 -1100 {lab=Control}
N 190 -1170 400 -1170 {lab=Control}
N 190 -1170 190 -850 {lab=Control}
N 190 -850 220 -850 {lab=Control}
N 260 -690 320 -690 {lab=GND}
N 260 -640 320 -640 {lab=GND}
N 260 -730 320 -730 {lab=vdd}
N 190 -850 190 -580 {lab=Control}
N 190 -580 400 -580 {lab=Control}
N 260 -1020 320 -1020 {lab=vref}
N 260 -970 320 -970 {lab=GND}
N 260 -1060 320 -1060 {lab=vdd}
N 150 -850 190 -850 {lab=Control}
N 260 -920 260 -910 {lab=vdd}
N 260 -790 260 -780 {lab=GND}
N 570 -860 570 -840 {lab=Vo}
N 540 -860 570 -860 {lab=Vo}
N 570 -780 570 -770 {lab=GND}
C {vsource.sym} 40 -570 0 0 {name=V1 value=0.6}
C {vsource.sym} 40 -420 0 0 {name=V2 value="PULSE(0 1.2 0 1u 1u 10u 20u)"}
C {devices/code_shown.sym} 250 -540 0 0 {name=NGSPICE
only_toplevel=true
value="
.control
save all
tran 1u 100u
write T_gate_tb.raw
.endc
" }
C {devices/code_shown.sym} 240 -370 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value=".lib cornerMOSlv.lib mos_tt
"}
C {gnd.sym} 40 -360 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 40 -630 0 0 {name=p1 sig_type=std_logic lab=vref}
C {lab_pin.sym} 40 -480 0 0 {name=p2 sig_type=std_logic lab=Control}
C {gnd.sym} 40 -510 0 0 {name=l2 lab=GND}
C {vsource.sym} 40 -720 0 0 {name=V3 value=1.2}
C {lab_pin.sym} 40 -780 0 0 {name=p3 sig_type=std_logic lab=vdd}
C {gnd.sym} 40 -660 0 0 {name=l3 lab=GND}
C {iopin.sym} 590 -860 0 0 {name=p5 lab=Vo}
C {launcher.sym} 820 -310 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/T_gate_tb.raw tran"
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 240 -850 0 0 {name=x3}
C {gnd.sym} 260 -690 0 0 {name=l5 lab=GND}
C {gnd.sym} 260 -640 0 0 {name=l6 lab=GND}
C {lab_pin.sym} 260 -730 0 0 {name=p6 sig_type=std_logic lab=vdd}
C {gnd.sym} 260 -970 0 0 {name=l8 lab=GND}
C {lab_pin.sym} 260 -1060 0 0 {name=p7 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 260 -1020 0 0 {name=p8 sig_type=std_logic lab=vref}
C {lab_pin.sym} 150 -850 0 0 {name=p9 sig_type=std_logic lab=Control}
C {lab_pin.sym} 260 -920 0 0 {name=p4 sig_type=std_logic lab=vdd}
C {gnd.sym} 260 -780 0 0 {name=l4 lab=GND}
C {capa.sym} 570 -810 0 0 {name=C1
m=1
value=7p
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 570 -770 0 0 {name=l7 lab=GND}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 400 -1020 0 0 {name=x1}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 400 -690 0 0 {name=x2}

193
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/python/generate_sym.py Normal file
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@ -0,0 +1,193 @@
import re
import sys
import os
def parse_verilog(verilog_file):
"""Extract module name, inputs, and outputs from a Verilog file while expanding bus signals."""
with open(verilog_file, "r") as f:
code = f.read()
module_match = re.search(r"module\s+(\w+)\s*\(", code)
if not module_match:
raise ValueError("No module found in the Verilog file.")
module_name = module_match.group(1)
# Remove comments
code = re.sub(r"//.*", "", code)
# Adjusted regex to capture bus definitions properly
ports = re.findall(r"(input|output)\s*(?:wire|reg)?\s*(\[\d+:\d+\])?\s*(\w+)", code)
inputs = []
outputs = []
for direction, bus, name in ports:
if bus:
# Extract bus range
msb, lsb = map(int, re.findall(r"\d+", bus))
indices = range(msb, lsb - 1, -1) if msb >= lsb else range(msb, lsb + 1)
expanded_names = [f"{name}{i}" for i in indices] # Adjusted naming convention
else:
expanded_names = [name]
if direction == "input":
inputs.extend(expanded_names)
else:
outputs.extend(expanded_names)
# Separate outputs into non-numeric and numeric groups
non_numeric_outputs = [o for o in outputs if not re.search(r'\d+', o)]
numeric_outputs = [o for o in outputs if re.search(r'\d+', o)]
# Sort numeric outputs by base name and index, ensuring 'p' comes before 'n'
numeric_outputs.sort(key=lambda x: (
re.sub(r'\d+', '', x).replace('p', '0').replace('n', '1'), # Prioritize 'p' over 'n'
int(re.search(r'\d+', x).group())
))
# Combine non-numeric outputs first, followed by sorted numeric outputs
outputs = non_numeric_outputs + numeric_outputs
# Reverse the order of outputs so that it starts from D_N to D_0
outputs = outputs[::-1] # Reverse the output order to D_N to D_0
return module_name, inputs, outputs
Version_text = """v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}"""
def generate_xschem_symbol(verilog_file, output_sym):
"""Generate an Xschem symbol (.sym) for the given Verilog module with expanded bus signals."""
module_name, inputs, outputs = parse_verilog(verilog_file)
# Sort inputs and outputs to ensure bus signals are in descending order
def sort_bus_signals(signals):
"""Sort bus signals in descending order for proper formatting."""
numeric_signals = [s for s in signals if re.search(r'\d+', s)]
non_numeric_signals = [s for s in signals if not re.search(r'\d+', s)]
# Sort numeric signals by base name and descending index
numeric_signals.sort(key=lambda x: (
re.sub(r'\d+', '', x), # Base name
-int(re.search(r'\d+', x).group()) # Descending numeric index
))
# Combine non-numeric signals first, followed by sorted numeric signals
return non_numeric_signals + numeric_signals
inputs = sort_bus_signals(inputs)
outputs = sort_bus_signals(outputs)
# Generate the format string dynamically
format_inputs = " ".join(f"@@{p}" for p in inputs)
format_outputs = " ".join(f"@@{p}" for p in outputs)
symbol = [
Version_text,
"G {}",
"K {type=delay",
"verilog_ignore=true",
"vhdl_ignore=true",
f'format="@name [ {format_inputs} ] [ {format_outputs} ] null @dut',
'.model @dut @d_cosim_model simulation=@model"',
"template=\"name=adut",
"dut=dut",
"d_cosim_model= d_cosim",
f"model=./{os.path.basename(verilog_file)[:-2]}.so\" }}",
"V {}", "S {}", "E {}"
]
pin_distance, width, offset_factor = 20, 100, 30
total_pins = len(inputs) + len(outputs)
height_input_side = len(inputs) * pin_distance
height_output_side = len(outputs) * pin_distance
total_height = max(height_input_side, height_output_side)
start_y_input = -height_input_side // 2 + pin_distance // 2
start_y_output = -height_output_side // 2 + pin_distance // 2
# Define the structure of lines and boxes as per original .sym. Starting by creating the L lines
for i, pin_name in enumerate(inputs):
y = start_y_input + pin_distance * i
symbol.append(f"L 4 -{width//2 + 2.5 + offset_factor} {y} -{width//2 - 2.5 + offset_factor} {y} {{}}")
for i, pin_name in enumerate(outputs):
y = start_y_output + pin_distance * i
symbol.append(f"L 4 {width//2 + 2.5 + offset_factor} {y} {width//2 - 2.5 + offset_factor} {y} {{}}")
for i, pin_name in enumerate(inputs):
y = start_y_input + pin_distance * i
symbol.append(f"B 5 -{width//2 + 2.5 + offset_factor} {y-2.5} -{width//2 - 2.5 + offset_factor} {y+2.5} {{name={pin_name} dir=in verilog_type=wire propag=0}}")
for i, pin_name in enumerate(outputs):
y = start_y_output + pin_distance * i
symbol.append(f"B 5 {width//2 - 2.5 + offset_factor} {y-2.5} {width//2 + 2.5 + offset_factor} {y+2.5} {{name={pin_name} dir=out verilog_type=wire propag=1}}")
# Module name at the top of the symbol
symbol.append(f'T {{@name}} 0 {total_height//2 + 5} 0 0 0.12 0.12 {{}}')
# Module name at the bottom of the symbol
symbol.append(f'T {{@d_cosim_model}} 0 {-total_height//2 + 5} 0 0 0.12 0.12 {{}}')
# Printing pin names on the symbol with proper orientation
for i, pin_name in enumerate(inputs):
y = start_y_input + pin_distance * i
symbol.append(f"T {{{pin_name}}} -90 {y-2.5} 0 1 0.12 0.12 {{}}") # Negative for input side
for i, pin_name in enumerate(outputs):
y = start_y_output + pin_distance * i
symbol.append(f"T {{{pin_name}}} 90 {y-2.5} 0 0 0.12 0.12 {{}}") # Positive for output side
# Lines that form the box around the symbol
symbol.append(f'L 4 {width//2} -{total_height//2} {width//2} {total_height//2} {{}}')
symbol.append(f'L 4 -{width//2} -{total_height//2} -{width//2} {total_height//2} {{}}')
symbol.append(f'L 4 -{width//2} {total_height//2} {width//2} {total_height//2} {{}}')
symbol.append(f'L 4 -{width//2} -{total_height//2} {width//2} -{total_height//2} {{}}')
with open(output_sym, "w") as f:
f.write("\n".join(symbol))
print(f"Xschem symbol written to {output_sym}")
def main():
"""Main function to process Verilog and generate the symbol."""
if len(sys.argv) != 3:
print("\nUsage: python generate_sym.py <verilog_file> <symbol_file>")
print("Example: python generate_sym.py control.v test.sym\n")
sys.exit(1)
verilog_file, sym_file = sys.argv[1:3]
try:
module_name, inputs, outputs = parse_verilog(verilog_file)
print(f"Parsed module: {module_name}\nInputs: {inputs}\nOutputs: {outputs}")
generate_xschem_symbol(verilog_file, sym_file)
except Exception as e:
print(f"Error: {e}")
sys.exit(1)
if __name__ == "__main__":
main()

12
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/Makefile → modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/verilog/Makefile
View File

@ -4,12 +4,12 @@ IVERILOG = iverilog
VVP = vvp
GTKWAVE = gtkwave
NGSPICE = ngspice
OUTPUT = sar_algo.out
MIXED = sar_algo.so
MIXED_OBJ = sar_algo_obj_dir
VCD_FILE = sar_algo_tb.vcd
SRC_FILES = sar_algo.v sar_algo_tb.v
NGSPICE_FILE = sar_algo.v
OUTPUT = sar_logic.out
MIXED = sar_logic.so
MIXED_OBJ = sar_logic_obj_dir
VCD_FILE = sar_logic_tb.vcd
SRC_FILES = sar_logic.v sar_logic_tb.v
NGSPICE_FILE = sar_logic.v
DEST_DIR = ../xschem/simulations
# Default target
all: run_wave

16
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/verilog/conf.gtkw → modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/verilog/conf.gtkw
View File

@ -2,10 +2,10 @@
[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
[*] Mon Sep 30 13:11:15 2024
[*]
[dumpfile] "/home/herman/tmp/AnalogMux-Workshop/design_data/verilog/basicBlock/basic_tb.vcd"
[dumpfile] "sar_logic_tb.vcd"
[dumpfile_mtime] "Mon Sep 30 13:10:47 2024"
[dumpfile_size] 777
[savefile] "/home/herman/tmp/AnalogMux-Workshop/design_data/verilog/basicBlock/conf.gtkw"
[savefile] "conf.gtkw"
[timestart] 0
[size] 1906 985
[pos] -1 -1
@ -15,10 +15,14 @@
[sst_expanded] 1
[sst_vpaned_height] 291
@28
basic_tb.clk
basic_tb.rst
basic_tb.dout[1:0]
sar_logic_tb.Op
sar_logic_tb.Om
sar_logic_tb.B[6:0]
sar_logic_tb.BN[6:0]
sar_logic_tb.D[7:0]
sar_logic_tb.clk
sar_logic_tb.rst
sar_logic_tb.En
@29
basic_tb.din[1:0]
[pattern_trace] 1
[pattern_trace] 0

33
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/verilog/sar_logic.v Normal file
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@ -0,0 +1,33 @@
module sar_logic (
input wire clk,
input wire Op,
input wire En,
input wire Om,
input wire rst,
output reg [6:0] B, // 7-bit
output reg [6:0] BN, // 7-bit
output reg [7:0] D // 8-bit
);
reg [3:0] counter = 4'b0000; // 4-bit counter
always @(posedge clk) begin
if (rst) begin
B <= 7'b0000000;
BN <= 7'b0000000;
D <= 8'b00000000;
counter <= 4'b0000;
end else if (En && (Op ^ Om)) begin
if (counter < 7) begin
D <= D | ({7'b0, Op} << counter);
B[counter % 7] <= (Op) ? 1'b1 : 1'b0;
BN[counter % 7] <= (Om) ? 1'b1 : 1'b0;
counter <= counter + 1'b1;
end
end
end
endmodule

63
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/verilog/sar_logic_tb.v Normal file
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@ -0,0 +1,63 @@
`timescale 1ns/1ps
module sar_logic_tb();
// Inputs
reg clk;
reg rst;
reg Op;
reg Om;
reg En;
// Outputs
wire [6:0] B;
wire [6:0] BN;
wire [7:0] D;
// Instantiate the SAR Logic module
sar_logic uut (
.clk(clk),
.rst(rst),
.Op(Op),
.Om(Om),
.En(En),
.B(B),
.BN(BN),
.D(D)
);
// Clock generation
always #5 clk = ~clk;
// Test sequence
initial begin
$dumpfile("sar_logic_tb.vcd"); // Name of the VCD file
$dumpvars(0, sar_logic_tb); // Dump all variables in the testbench
// Initialize inputs
clk = 1'b0;
rst = 1'b1;
Op = 1'b0;
Om = 1'b0;
En = 1'b0;
// Apply reset
#20 rst = 1'b0;
En = 1'b1;
Op = 1'b1;
Om = 1'b0;
// Apply reset again
#80 rst = 1'b1;
#10 rst = 1'b0;
Op = 1'b0;
Om = 1'b1;
#70 rst = 1'b1;
// End of simulation
#100 $finish;
end
endmodule

0
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/xschem/adc_bridge1.sym → modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym
View File

0
modules/module_3_8_bit_SAR_ADC/part_2_algorithm/xschem/dac_bridge1.sym → modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym
View File

121
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/sar_logic.sym Normal file
View File

@ -0,0 +1,121 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@clk @@Op @@En @@Om @@rst ] [ @@B6 @@B5 @@B4 @@B3 @@B2 @@B1 @@B0 @@BN6 @@BN5 @@BN4 @@BN3 @@BN2 @@BN1 @@BN0 @@D7 @@D6 @@D5 @@D4 @@D3 @@D2 @@D1 @@D0 ] null @dut
.model @dut @d_cosim_model simulation=@model"
template="name=adut
dut=dut
d_cosim_model= d_cosim
model=./sar_logic.so" }
V {}
S {}
E {}
L 4 -82.5 -40 -77.5 -40 {}
L 4 -82.5 -20 -77.5 -20 {}
L 4 -82.5 0 -77.5 0 {}
L 4 -82.5 20 -77.5 20 {}
L 4 -82.5 40 -77.5 40 {}
L 4 82.5 -210 77.5 -210 {}
L 4 82.5 -190 77.5 -190 {}
L 4 82.5 -170 77.5 -170 {}
L 4 82.5 -150 77.5 -150 {}
L 4 82.5 -130 77.5 -130 {}
L 4 82.5 -110 77.5 -110 {}
L 4 82.5 -90 77.5 -90 {}
L 4 82.5 -70 77.5 -70 {}
L 4 82.5 -50 77.5 -50 {}
L 4 82.5 -30 77.5 -30 {}
L 4 82.5 -10 77.5 -10 {}
L 4 82.5 10 77.5 10 {}
L 4 82.5 30 77.5 30 {}
L 4 82.5 50 77.5 50 {}
L 4 82.5 70 77.5 70 {}
L 4 82.5 90 77.5 90 {}
L 4 82.5 110 77.5 110 {}
L 4 82.5 130 77.5 130 {}
L 4 82.5 150 77.5 150 {}
L 4 82.5 170 77.5 170 {}
L 4 82.5 190 77.5 190 {}
L 4 82.5 210 77.5 210 {}
B 5 -82.5 -42.5 -77.5 -37.5 {name=clk dir=in verilog_type=wire propag=0}
B 5 -82.5 -22.5 -77.5 -17.5 {name=Op dir=in verilog_type=wire propag=0}
B 5 -82.5 -2.5 -77.5 2.5 {name=En dir=in verilog_type=wire propag=0}
B 5 -82.5 17.5 -77.5 22.5 {name=Om dir=in verilog_type=wire propag=0}
B 5 -82.5 37.5 -77.5 42.5 {name=rst dir=in verilog_type=wire propag=0}
B 5 77.5 -212.5 82.5 -207.5 {name=B6 dir=out verilog_type=wire propag=1}
B 5 77.5 -192.5 82.5 -187.5 {name=B5 dir=out verilog_type=wire propag=1}
B 5 77.5 -172.5 82.5 -167.5 {name=B4 dir=out verilog_type=wire propag=1}
B 5 77.5 -152.5 82.5 -147.5 {name=B3 dir=out verilog_type=wire propag=1}
B 5 77.5 -132.5 82.5 -127.5 {name=B2 dir=out verilog_type=wire propag=1}
B 5 77.5 -112.5 82.5 -107.5 {name=B1 dir=out verilog_type=wire propag=1}
B 5 77.5 -92.5 82.5 -87.5 {name=B0 dir=out verilog_type=wire propag=1}
B 5 77.5 -72.5 82.5 -67.5 {name=BN6 dir=out verilog_type=wire propag=1}
B 5 77.5 -52.5 82.5 -47.5 {name=BN5 dir=out verilog_type=wire propag=1}
B 5 77.5 -32.5 82.5 -27.5 {name=BN4 dir=out verilog_type=wire propag=1}
B 5 77.5 -12.5 82.5 -7.5 {name=BN3 dir=out verilog_type=wire propag=1}
B 5 77.5 7.5 82.5 12.5 {name=BN2 dir=out verilog_type=wire propag=1}
B 5 77.5 27.5 82.5 32.5 {name=BN1 dir=out verilog_type=wire propag=1}
B 5 77.5 47.5 82.5 52.5 {name=BN0 dir=out verilog_type=wire propag=1}
B 5 77.5 67.5 82.5 72.5 {name=D7 dir=out verilog_type=wire propag=1}
B 5 77.5 87.5 82.5 92.5 {name=D6 dir=out verilog_type=wire propag=1}
B 5 77.5 107.5 82.5 112.5 {name=D5 dir=out verilog_type=wire propag=1}
B 5 77.5 127.5 82.5 132.5 {name=D4 dir=out verilog_type=wire propag=1}
B 5 77.5 147.5 82.5 152.5 {name=D3 dir=out verilog_type=wire propag=1}
B 5 77.5 167.5 82.5 172.5 {name=D2 dir=out verilog_type=wire propag=1}
B 5 77.5 187.5 82.5 192.5 {name=D1 dir=out verilog_type=wire propag=1}
B 5 77.5 207.5 82.5 212.5 {name=D0 dir=out verilog_type=wire propag=1}
T {@name} 0 225 0 0 0.12 0.12 {}
T {@d_cosim_model} 0 -215 0 0 0.12 0.12 {}
T {clk} -90 -42.5 0 1 0.12 0.12 {}
T {Op} -90 -22.5 0 1 0.12 0.12 {}
T {En} -90 -2.5 0 1 0.12 0.12 {}
T {Om} -90 17.5 0 1 0.12 0.12 {}
T {rst} -90 37.5 0 1 0.12 0.12 {}
T {B6} 90 -212.5 0 0 0.12 0.12 {}
T {B5} 90 -192.5 0 0 0.12 0.12 {}
T {B4} 90 -172.5 0 0 0.12 0.12 {}
T {B3} 90 -152.5 0 0 0.12 0.12 {}
T {B2} 90 -132.5 0 0 0.12 0.12 {}
T {B1} 90 -112.5 0 0 0.12 0.12 {}
T {B0} 90 -92.5 0 0 0.12 0.12 {}
T {BN6} 90 -72.5 0 0 0.12 0.12 {}
T {BN5} 90 -52.5 0 0 0.12 0.12 {}
T {BN4} 90 -32.5 0 0 0.12 0.12 {}
T {BN3} 90 -12.5 0 0 0.12 0.12 {}
T {BN2} 90 7.5 0 0 0.12 0.12 {}
T {BN1} 90 27.5 0 0 0.12 0.12 {}
T {BN0} 90 47.5 0 0 0.12 0.12 {}
T {D7} 90 67.5 0 0 0.12 0.12 {}
T {D6} 90 87.5 0 0 0.12 0.12 {}
T {D5} 90 107.5 0 0 0.12 0.12 {}
T {D4} 90 127.5 0 0 0.12 0.12 {}
T {D3} 90 147.5 0 0 0.12 0.12 {}
T {D2} 90 167.5 0 0 0.12 0.12 {}
T {D1} 90 187.5 0 0 0.12 0.12 {}
T {D0} 90 207.5 0 0 0.12 0.12 {}
L 4 50 -220 50 220 {}
L 4 -50 -220 -50 220 {}
L 4 -50 220 50 220 {}
L 4 -50 -220 50 -220 {}

484
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/sar_logic_tb.sch Normal file
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@ -0,0 +1,484 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
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B 2 1580 -860 2380 -470 {flags=graph
y1=0
y2=1.3
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unity=1
x1=0
x2=0.0002
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
color=4
node=clk}
B 2 2390 -1260 3190 -870 {flags=graph
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unity=1
x1=0
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divx=5
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dataset=-1
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logx=0
logy=0
color="4 5 17 7 8 12 18 20"
node="bn0
bn1
bn2
bn3
bn4
bn5
bn6
bn7"}
B 2 2390 -1670 3190 -1280 {flags=graph
y1=0
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ypos1=0
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divy=5
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unity=1
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color="7 6 4 12 13 10 17"
node="d0
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d3
d4
d5
d6
d7"}
B 2 1580 -1260 2380 -870 {flags=graph
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unity=1
x1=0
x2=0.0002
divx=5
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dataset=-1
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logx=0
logy=0
color=4
node=en}
B 2 1580 -1670 2380 -1280 {flags=graph
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divy=5
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unity=1
x1=0
x2=0.0002
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
color="7 8"
node="op
om"}
B 2 2390 -860 3190 -470 {flags=graph
y1=0
y2=1.3
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divy=5
subdivy=1
unity=1
x1=0
x2=0.0002
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
color="4 5 18 8 13 10 5 7"
node="b0
b1
b2
b3
b4
b5
b6
b7"}
B 2 760 -1670 1560 -1280 {flags=graph
y1=0
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ypos1=0
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divy=5
subdivy=1
unity=1
x1=0
x2=0.0002
divx=5
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dataset=-1
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logx=0
logy=0
color=4
node=rst}
T {Analog} 960 -1020 0 0 0.4 0.4 {}
T {Digital} 770 -1010 0 0 0.4 0.4 {}
N 670 -680 730 -680 {
lab=#net1}
N 340 -1070 340 -1060 {lab=Op}
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N 340 -780 340 -770 {lab=GND}
N 340 -960 340 -950 {lab=En}
N 340 -890 340 -880 {lab=GND}
N 340 -520 340 -510 {lab=GND}
N 340 -600 340 -580 {lab=rst}
N 670 -740 730 -740 {lab=#net2}
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N 670 -720 730 -720 {lab=#net4}
N 590 -680 610 -680 {lab=rst}
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N 590 -760 610 -760 {lab=clk}
N 670 -700 730 -700 {
lab=#net5}
N 610 -570 610 -540 {lab=clk_reserve}
N 610 -480 610 -470 {lab=GND}
N 1000 -930 1200 -930 {
lab=B5}
N 1000 -910 1200 -910 {lab=B4}
N 1000 -890 1200 -890 {lab=B3}
N 1000 -870 1200 -870 {lab=B2}
N 1000 -850 1200 -850 {lab=B1}
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N 890 -830 940 -830 {lab=#net11}
N 890 -810 940 -810 {lab=#net12}
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N 1000 -710 1200 -710 {lab=BN2}
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N 1000 -670 1200 -670 {lab=BN0}
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N 890 -650 940 -650 {lab=#net20}
N 1000 -630 1200 -630 {lab=D6}
N 1000 -610 1200 -610 {lab=D5}
N 890 -630 940 -630 {lab=#net21}
N 890 -610 940 -610 {lab=#net22}
N 1000 -590 1200 -590 {lab=D4}
N 1000 -570 1200 -570 {lab=D3}
N 890 -590 940 -590 {lab=#net23}
N 890 -570 940 -570 {lab=#net24}
N 1000 -550 1200 -550 {lab=D2}
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N 890 -550 940 -550 {lab=#net25}
N 890 -530 940 -530 {lab=#net26}
N 1000 -510 1200 -510 {lab=D0}
N 890 -510 940 -510 {lab=#net27}
N 340 -720 340 -710 {lab=clk}
N 340 -650 340 -640 {lab=GND}
C {devices/code_shown.sym} 620 -1130 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.control
save all
tran 1u 200u
write sar_logic.raw
.endc
"}
C {devices/title.sym} 270 -300 0 0 {name=l5 author="Copyright 2024 IHP PDK Authors"}
C {adc_bridge1.sym} 640 -700 0 0 {name=A4
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {devices/launcher.sym} 887.5 -440 0 0 {name=h1
descr="load waves Ctrl + left click"
tclcommand="xschem raw_read $netlist_dir/sar_logic.raw tran"
}
C {adc_bridge1.sym} 640 -680 0 0 {name=A3
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {sar_logic.sym} 810 -720 0 0 {name=adut
dut=dut
d_cosim_model= d_cosim
model=./sar_logic.so}
C {dac_bridge1.sym} 970 -930 0 0 {name=A5
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {dac_bridge1.sym} 970 -910 0 0 {name=A1
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {adc_bridge1.sym} 640 -760 0 0 {name=A6
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {adc_bridge1.sym} 640 -740 0 0 {name=A7
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {adc_bridge1.sym} 640 -720 0 0 {name=A8
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {dac_bridge1.sym} 970 -890 0 0 {name=A9
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {dac_bridge1.sym} 970 -870 0 0 {name=A10
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {dac_bridge1.sym} 970 -850 0 0 {name=A11
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/vsource.sym} 340 -920 0 0 {name=V3 value="dc 0 ac 0 PULSE(1.2 0 0 1n 1n 30u 1m)"}
C {devices/gnd.sym} 340 -990 0 0 {name=l2 lab=GND}
C {devices/lab_pin.sym} 340 -1070 2 0 {name=p5 sig_type=std_logic lab=Op}
C {devices/gnd.sym} 340 -770 0 0 {name=l7 lab=GND}
C {devices/lab_pin.sym} 340 -850 2 0 {name=p8 sig_type=std_logic lab=Om}
C {devices/lab_pin.sym} 340 -960 2 0 {name=p9 sig_type=std_logic lab=En}
C {devices/gnd.sym} 340 -880 0 0 {name=l8 lab=GND}
C {devices/lab_pin.sym} 340 -600 2 0 {name=p11 sig_type=std_logic lab=rst}
C {devices/gnd.sym} 340 -510 0 0 {name=l10 lab=GND}
C {devices/lab_pin.sym} 1200 -930 2 0 {name=p6 sig_type=std_logic lab=B5}
C {devices/lab_pin.sym} 1200 -870 2 0 {name=p7 sig_type=std_logic lab=B2}
C {devices/lab_pin.sym} 1200 -890 2 0 {name=p15 sig_type=std_logic lab=B3}
C {devices/lab_pin.sym} 1200 -910 2 0 {name=p16 sig_type=std_logic lab=B4}
C {devices/vsource.sym} 340 -1030 0 0 {name=V6 value="dc 0 ac 0 PULSE(1.2 0 100u 1n 1n 500u 1m)"}
C {devices/vsource.sym} 340 -550 0 0 {name=V2 value="dc 0 ac 0 PULSE(0 1.2 100u 1n 1n 10u 1m)"}
C {devices/vsource.sym} 610 -510 0 0 {name=V1 value="dc 0 ac 0 pulse(0 1 0 1n 1n 5n 10n)"}
C {devices/gnd.sym} 610 -470 0 0 {name=l3 lab=GND}
C {devices/lab_pin.sym} 610 -570 2 0 {name=p17 sig_type=std_logic lab=clk_reserve}
C {devices/lab_pin.sym} 590 -680 2 1 {name=p2 sig_type=std_logic lab=rst}
C {devices/lab_pin.sym} 590 -760 2 1 {name=p12 sig_type=std_logic lab=clk}
C {devices/vsource.sym} 340 -810 0 0 {name=V5 value="dc 0 ac 0 PULSE(0 1.2 100u 1n 1n 500u 1m)"}
C {devices/lab_pin.sym} 590 -740 2 1 {name=p3 sig_type=std_logic lab=Op}
C {devices/lab_pin.sym} 590 -720 2 1 {name=p13 sig_type=std_logic lab=En}
C {devices/lab_pin.sym} 590 -700 2 1 {name=p14 sig_type=std_logic lab=Om}
C {dac_bridge1.sym} 970 -830 0 0 {name=A12
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -850 2 0 {name=p18 sig_type=std_logic lab=B1}
C {dac_bridge1.sym} 970 -810 0 0 {name=A13
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -830 2 0 {name=p19 sig_type=std_logic lab=B0}
C {dac_bridge1.sym} 970 -790 0 0 {name=A14
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -810 2 0 {name=p20 sig_type=std_logic lab=BN7}
C {dac_bridge1.sym} 970 -770 0 0 {name=A15
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -790 2 0 {name=p21 sig_type=std_logic lab=BN6}
C {dac_bridge1.sym} 970 -750 0 0 {name=A16
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -770 2 0 {name=p22 sig_type=std_logic lab=BN5}
C {dac_bridge1.sym} 970 -730 0 0 {name=A17
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -750 2 0 {name=p23 sig_type=std_logic lab=BN4}
C {dac_bridge1.sym} 970 -710 0 0 {name=A18
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -730 2 0 {name=p24 sig_type=std_logic lab=BN3}
C {dac_bridge1.sym} 970 -690 0 0 {name=A19
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -710 2 0 {name=p25 sig_type=std_logic lab=BN2}
C {dac_bridge1.sym} 970 -670 0 0 {name=A20
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -690 2 0 {name=p26 sig_type=std_logic lab=BN1}
C {dac_bridge1.sym} 970 -650 0 0 {name=A21
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -670 2 0 {name=p27 sig_type=std_logic lab=BN0}
C {dac_bridge1.sym} 970 -630 0 0 {name=A22
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -650 2 0 {name=p28 sig_type=std_logic lab=D7}
C {dac_bridge1.sym} 970 -610 0 0 {name=A23
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -630 2 0 {name=p29 sig_type=std_logic lab=D6}
C {dac_bridge1.sym} 970 -590 0 0 {name=A24
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -610 2 0 {name=p30 sig_type=std_logic lab=D5}
C {dac_bridge1.sym} 970 -570 0 0 {name=A25
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -590 2 0 {name=p31 sig_type=std_logic lab=D4}
C {dac_bridge1.sym} 970 -550 0 0 {name=A26
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -570 2 0 {name=p32 sig_type=std_logic lab=D3}
C {dac_bridge1.sym} 970 -530 0 0 {name=A27
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -550 2 0 {name=p33 sig_type=std_logic lab=D2}
C {dac_bridge1.sym} 970 -510 0 0 {name=A28
dac=dac1
dac_bridge_model=dac_bridge
in_low=0.0
in_high=1.2
}
C {devices/lab_pin.sym} 1200 -530 2 0 {name=p34 sig_type=std_logic lab=D1}
C {devices/lab_pin.sym} 1200 -510 2 0 {name=p35 sig_type=std_logic lab=D0}
C {devices/gnd.sym} 340 -640 0 0 {name=l1 lab=GND}
C {devices/lab_pin.sym} 340 -720 2 0 {name=p1 sig_type=std_logic lab=clk}
C {devices/vsource.sym} 340 -680 0 0 {name=V4 value="dc 0 ac 0 PULSE(0 1.2 0 10p 10p 5u 10u)"}

232
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sch Normal file
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@ -0,0 +1,232 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 230 -790 230 -760 {lab=vdd}
N 230 -790 430 -790 {lab=vdd}
N 430 -790 430 -760 {lab=vdd}
N 270 -730 430 -610 {lab=#net1}
N 430 -700 430 -610 {lab=#net1}
N 230 -700 230 -610 {lab=#net2}
N 230 -610 390 -730 {lab=#net2}
N 430 -790 610 -790 {lab=vdd}
N 610 -790 610 -760 {lab=vdd}
N 610 -640 610 -590 {lab=#net3}
N 610 -640 890 -640 {lab=#net3}
N 610 -790 760 -790 {lab=vdd}
N 760 -790 760 -760 {lab=vdd}
N 710 -730 720 -730 {lab=gp}
N 550 -730 570 -730 {lab=#net2}
N 760 -440 760 -410 {lab=#net4}
N 760 -550 760 -500 {lab=#net5}
N 430 -610 430 -590 {lab=#net1}
N 230 -610 230 -590 {lab=#net2}
N 610 -530 610 -510 {lab=#net6}
N 610 -510 1010 -510 {lab=#net6}
N 760 -550 1040 -550 {lab=#net5}
N 760 -700 760 -550 {lab=#net5}
N 610 -700 610 -640 {lab=#net3}
N 920 -640 920 -630 {lab=#net3}
N 890 -630 920 -630 {lab=#net3}
N 890 -640 890 -630 {lab=#net3}
N 1100 -510 1120 -510 {lab=vi}
N 1150 -640 1170 -640 {lab=#net7}
N 1230 -640 1260 -640 {lab=#net8}
N 1320 -640 1340 -640 {lab=gnd}
N 1150 -640 1150 -550 {lab=#net7}
N 950 -640 1150 -640 {lab=#net7}
N 1100 -510 1100 -410 {lab=vi}
N 1070 -510 1100 -510 {lab=vi}
N 230 -530 230 -160 {lab=clk_not}
N 430 -530 430 -410 {lab=#net9}
N 610 -510 610 -260 {lab=#net6}
N 570 -380 570 -160 {lab=clk_not}
N 570 -380 720 -380 {lab=clk_not}
N 610 -200 610 -160 {lab=gnd}
N 330 -270 370 -270 {lab=vdd}
N 490 -270 510 -270 {lab=gnd}
N 430 -230 430 -160 {lab=clk_not}
N 230 -160 430 -160 {lab=clk_not}
N 920 -720 920 -680 {lab=#net10}
N 760 -350 760 -320 {lab=gnd}
N 1180 -510 1240 -510 {lab=vo}
N 760 -790 1060 -790 {lab=vdd}
N 1060 -660 1060 -650 {lab=gnd}
N 1060 -790 1060 -780 {lab=vdd}
N 1060 -790 1200 -790 {lab=vdd}
N 1200 -790 1200 -680 {lab=vdd}
N 1100 -720 1120 -720 {lab=gp}
N 1290 -710 1290 -680 {lab=clk_not}
N 760 -470 820 -470 {lab=gnd}
N 760 -380 820 -380 {lab=gnd}
N 430 -730 470 -730 {lab=gnd}
N 180 -730 230 -730 {lab=gnd}
N 1150 -510 1150 -450 {lab=gnd}
N 1040 -510 1040 -450 {lab=gnd}
N 760 -730 810 -730 {lab=vdd}
N 610 -730 650 -730 {lab=gnd}
N 1200 -640 1200 -600 {lab=gnd}
N 1290 -640 1290 -600 {lab=gnd}
N 610 -230 710 -230 {lab=gnd}
N 390 -750 390 -730 {lab=#net2}
N 390 -750 550 -750 {lab=#net2}
N 550 -750 550 -730 {lab=#net2}
N 980 -390 980 -360 {lab=vdd}
N 980 -240 980 -210 {lab=gnd}
N 1120 -300 1150 -300 {lab=clk_not}
N 910 -300 940 -300 {lab=clk}
N 430 -160 570 -160 {lab=clk_not}
N 690 -470 720 -470 {lab=vdd}
C {sg13g2_pr/sg13_lv_nmos.sym} 410 -730 0 0 {name=M1
l=0.13u
w=1.3u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 250 -730 0 1 {name=M3
l=0.13u
w=1.3u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 920 -660 3 1 {name=M4
l=0.13u
w=500n
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 590 -730 0 0 {name=M2
l=0.13u
w=1.3u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 740 -730 0 0 {name=M6
l=130n
w=500n
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 740 -470 0 0 {name=M5
l=0.13u
w=3u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 740 -380 0 0 {name=M7
l=0.13u
w=3u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/cap_cmim.sym} 230 -560 0 0 {name=C5
model=cap_cmim
w=4.665e-6
l=6.99e-6
m=1
spiceprefix=X}
C {sg13g2_pr/cap_cmim.sym} 610 -560 0 0 {name=C6
model=cap_cmim
w=11.485e-6
l=11.485e-6
m=1
spiceprefix=X}
C {sg13g2_pr/sg13_lv_nmos.sym} 1040 -530 3 1 {name=M8
l=0.13u
w=5u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 1150 -530 1 0 {name=M9
l=0.13u
w=5u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 1200 -660 1 0 {name=M10
l=0.13u
w=500n
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 1290 -660 1 0 {name=M11
l=0.13u
w=500n
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 590 -230 0 0 {name=M12
l=0.13u
w=1.3u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {iopin.sym} 570 -860 0 0 {name=p2 lab=gnd}
C {iopin.sym} 630 -860 0 0 {name=p3 lab=vdd}
C {iopin.sym} 690 -860 0 0 {name=p4 lab=vi}
C {iopin.sym} 750 -860 0 0 {name=p5 lab=vo}
C {lab_pin.sym} 330 -270 0 0 {name=p1 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 230 -790 0 0 {name=p6 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 810 -730 0 1 {name=p7 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 820 -380 0 1 {name=p8 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 820 -470 0 1 {name=p9 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 710 -230 0 1 {name=p10 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 470 -730 0 1 {name=p11 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 180 -730 0 0 {name=p12 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1290 -600 3 0 {name=p13 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1200 -600 1 1 {name=p14 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1150 -450 1 1 {name=p15 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1040 -450 1 1 {name=p16 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1100 -410 1 1 {name=p17 sig_type=std_logic lab=vi}
C {lab_pin.sym} 1240 -510 2 0 {name=p18 sig_type=std_logic lab=vo}
C {lab_pin.sym} 1290 -710 2 0 {name=p19 sig_type=std_logic lab=clk_not}
C {lab_pin.sym} 230 -160 2 1 {name=p20 sig_type=std_logic lab=clk_not}
C {lab_pin.sym} 510 -270 0 1 {name=p21 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 650 -730 0 1 {name=p23 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 760 -320 0 1 {name=p24 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 710 -730 3 0 {name=p25 sig_type=std_logic lab=gp}
C {lab_pin.sym} 1120 -720 3 0 {name=p26 sig_type=std_logic lab=gp}
C {iopin.sym} 800 -860 0 0 {name=p27 lab=clk}
C {lab_pin.sym} 1150 -300 0 1 {name=p28 sig_type=std_logic lab=clk_not}
C {lab_pin.sym} 910 -300 0 0 {name=p29 sig_type=std_logic lab=clk}
C {lab_pin.sym} 980 -390 0 0 {name=p30 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 980 -210 0 0 {name=p31 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1340 -640 0 1 {name=p32 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 610 -160 0 1 {name=p33 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 690 -470 0 0 {name=p34 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 1060 -650 0 1 {name=p35 sig_type=std_logic lab=gnd}
C {sg13g2_pr/cap_cmim.sym} 430 -560 0 0 {name=C1
model=cap_cmim
w=4.665e-6
l=6.99e-6
m=1
spiceprefix=X}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 430 -250 3 0 {name=x1}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 1080 -720 0 1 {name=x2}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 960 -300 0 0 {name=x3}

32
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v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -50 0 -7.5 0 {}
L 4 40 0 82.5 0 {}
L 4 0 -15 32.5 -0 {}
L 7 20 50 20 70 {}
L 7 -70 0 -50 0 {}
L 7 80 0 100 0 {}
L 7 80 50 80 70 {}
L 7 -40 50 -40 70 {}
B 5 17.5 67.5 22.5 72.5 {name=vdd dir=inout}
B 5 -72.5 -2.5 -67.5 2.5 {name=vi dir=inout}
B 5 97.5 -2.5 102.5 2.5 {name=vo dir=inout}
B 5 77.5 67.5 82.5 72.5 {name=clk dir=inout}
B 5 -42.5 67.5 -37.5 72.5 {name=gnd dir=inout}
A 4 -3.75 0 3.535533905932738 315 360 {}
A 4 36.25 0 3.535533905932738 315 360 {}
P 4 5 -50 50 -40 50 -40 50 0 50 90 50 {}
T {@symname} -50 4 0 0 0.3 0.3 {}
T {@name} 55 -42 0 0 0.2 0.2 {}
T {vdd} 24 45 1 1 0.2 0.2 {}
T {vi} -45 -6 2 1 0.2 0.2 {}
T {vo} 75 -24 0 1 0.2 0.2 {}
T {clk} 84 45 1 1 0.2 0.2 {}
T {gnd} -36 45 1 1 0.2 0.2 {}

40
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sch Normal file
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v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 270 -160 270 -150 {lab=vo}
N 270 -280 270 -240 {lab=vdd}
N 270 -90 270 -50 {lab=gnd}
N 200 -210 230 -210 {lab=vi}
N 200 -160 200 -120 {lab=vi}
N 200 -120 230 -120 {lab=vi}
N 270 -160 370 -160 {lab=vo}
N 270 -180 270 -160 {lab=vo}
N 170 -160 200 -160 {lab=vi}
N 200 -210 200 -160 {lab=vi}
N 270 -120 350 -120 {lab=gnd}
N 270 -210 340 -210 {lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 250 -210 0 0 {name=M5
l=130n
w=800n
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 250 -120 0 0 {name=M7
l=130n
w=400n
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {iopin.sym} 170 -160 0 1 {name=p1 lab=vi}
C {iopin.sym} 370 -160 0 0 {name=p2 lab=vo}
C {iopin.sym} 270 -50 0 0 {name=p3 lab=gnd}
C {iopin.sym} 270 -280 0 0 {name=p4 lab=vdd}
C {lab_pin.sym} 340 -210 0 1 {name=p5 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 350 -120 0 1 {name=p6 sig_type=std_logic lab=gnd}

25
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym Normal file
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@ -0,0 +1,25 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 7 20 -60 20 -40 {}
L 7 -20 0 0 0 {}
L 7 140 0 160 0 {}
L 7 20 40 20 60 {}
B 5 17.5 -62.5 22.5 -57.5 {name=vdd dir=inout}
B 5 -22.5 -2.5 -17.5 2.5 {name=vi dir=inout}
B 5 157.5 -2.5 162.5 2.5 {name=vo dir=inout}
B 5 17.5 57.5 22.5 62.5 {name=gnd dir=inout}
A 4 137.5 0 7.071067811865476 135 360 {}
P 4 5 130 0 0 -50 0 50 130 0 130 0 {}
T {@symname} 16 -6 0 0 0.3 0.3 {}
T {@name} 75 -32 0 0 0.2 0.2 {}
T {vdd} 16 -35 3 1 0.2 0.2 {}
T {vi} 5 4 2 1 0.2 0.2 {}
T {vo} 125 -9 0 1 0.2 0.2 {}
T {gnd} 24 35 1 1 0.2 0.2 {}

101
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v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 620 -870 1420 -470 {flags=graph
y1=-0.0041666666
y2=0.0058333334
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0.0010238745
x2=0.0024868745
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vo
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
B 2 620 -460 1420 -60 {flags=graph
y1=0.00069444443
y2=0.010694444
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0.0010238745
x2=0.0024868745
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=vin
color=4
dataset=-1
unitx=1
logx=0
logy=0
}
N 300 -360 300 -300 {lab=GND}
N 60 -430 60 -400 {lab=clk}
N 60 -340 60 -320 {lab=GND}
N 60 -570 60 -540 {lab=vin}
N 60 -480 60 -460 {lab=GND}
N 500 -430 510 -430 {lab=vo}
N 230 -430 270 -430 {lab=vin}
N 60 -710 60 -680 {lab=vdd}
N 60 -620 60 -600 {lab=GND}
N 420 -360 420 -290 {lab=clk}
N 360 -360 360 -290 {lab=vdd}
N 500 -340 500 -300 {lab=GND}
N 500 -430 500 -400 {lab=vo}
N 440 -430 500 -430 {lab=vo}
C {devices/code_shown.sym} 0 -80 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value=".lib cornerMOSlv.lib mos_tt
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
"}
C {devices/code_shown.sym} 0 -250 0 0 {name=NGSPICE
only_toplevel=true
value="
.control
save all
tran 100u 1.463m
write test_bootstrap.raw
.endc
" }
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sym} 340 -430 0 0 {name=x1}
C {vsource.sym} 60 -370 0 0 {name=V1 value="PULSE(0 5 0 1n 1n 0.5u 1u)"}
C {gnd.sym} 60 -320 0 1 {name=l2 lab=GND}
C {lab_pin.sym} 60 -430 0 0 {name=p1 sig_type=std_logic lab=clk}
C {vsource.sym} 60 -510 0 0 {name=V2 value="SIN(0.6 0.6 683 0 0 0)"}
C {gnd.sym} 60 -460 0 1 {name=l3 lab=GND}
C {lab_pin.sym} 60 -570 0 0 {name=p2 sig_type=std_logic lab=vin}
C {iopin.sym} 510 -430 0 0 {name=p3 lab=vo}
C {lab_pin.sym} 230 -430 0 0 {name=p4 sig_type=std_logic lab=vin}
C {vsource.sym} 60 -650 0 0 {name=V3 value=1.2}
C {gnd.sym} 60 -600 0 1 {name=l4 lab=GND}
C {lab_pin.sym} 60 -710 0 0 {name=p5 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 420 -290 0 0 {name=p6 sig_type=std_logic lab=clk}
C {lab_pin.sym} 360 -290 0 0 {name=p7 sig_type=std_logic lab=vdd}
C {gnd.sym} 300 -300 0 1 {name=l5 lab=GND}
C {launcher.sym} 470 -160 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/test_bootstrap.raw tran"
}
C {capa.sym} 500 -370 0 0 {name=C1
m=1
value=7p
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 500 -300 0 1 {name=l1 lab=GND}

75
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v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 280 -100 340 -100 {lab=gnd}
N 280 -190 340 -190 {lab=gnd}
N 280 -160 280 -130 {lab=#net1}
N 280 -230 280 -220 {lab=Vo}
N 280 -250 400 -250 {lab=Vo}
N 160 -250 280 -250 {lab=Vo}
N 160 -290 160 -250 {lab=Vo}
N 400 -290 400 -250 {lab=Vo}
N 160 -400 160 -350 {lab=vdd}
N 280 -400 400 -400 {lab=vdd}
N 400 -400 400 -350 {lab=vdd}
N 400 -320 460 -320 {lab=vdd}
N 160 -320 220 -320 {lab=vdd}
N 90 -320 120 -320 {lab=A}
N 330 -320 360 -320 {lab=B}
N 210 -190 240 -190 {lab=A}
N 210 -100 240 -100 {lab=B}
N 280 -70 280 -40 {lab=gnd}
N 280 -430 280 -400 {lab=vdd}
N 160 -400 280 -400 {lab=vdd}
N 280 -230 470 -230 {lab=Vo}
N 280 -250 280 -230 {lab=Vo}
C {sg13g2_pr/sg13_lv_pmos.sym} 140 -320 0 0 {name=M5
l=0.13u
w=0.5u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 260 -190 0 0 {name=M6
l=0.13u
w=0.25u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_nmos.sym} 260 -100 0 0 {name=M1
l=0.13u
w=0.25u
ng=1
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 380 -320 0 0 {name=M2
l=0.13u
w=0.5u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 90 -320 0 0 {name=p1 sig_type=std_logic lab=A}
C {lab_pin.sym} 330 -320 0 0 {name=p2 sig_type=std_logic lab=B}
C {lab_pin.sym} 280 -430 0 0 {name=p3 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 210 -100 0 0 {name=p5 sig_type=std_logic lab=B}
C {lab_pin.sym} 210 -190 0 0 {name=p6 sig_type=std_logic lab=A}
C {lab_pin.sym} 340 -190 0 1 {name=p7 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 340 -100 0 1 {name=p8 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 280 -40 0 1 {name=p4 sig_type=std_logic lab=gnd}
C {iopin.sym} 280 -450 0 0 {name=p9 lab=vdd}
C {iopin.sym} 280 -10 0 0 {name=p10 lab=gnd}
C {lab_pin.sym} 220 -320 0 1 {name=p13 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 460 -320 0 1 {name=p14 sig_type=std_logic lab=vdd}
C {ipin.sym} 110 -170 0 0 {name=p15 lab=A}
C {opin.sym} 470 -230 0 0 {name=p16 lab=Vo}
C {ipin.sym} 110 -200 0 0 {name=p17 lab=B}

28
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@ -0,0 +1,28 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 60 -10 80 -10 {}
L 4 -150 20 -130 20 {}
L 4 -150 -40 -130 -40 {}
L 7 -60 -90 -60 -70 {}
L 7 -60 50 -60 70 {}
B 5 -62.5 -92.5 -57.5 -87.5 {name=vdd dir=inout}
B 5 77.5 -12.5 82.5 -7.5 {name=Vo dir=out}
B 5 -152.5 17.5 -147.5 22.5 {name=B dir=in}
B 5 -152.5 -42.5 -147.5 -37.5 {name=A dir=in}
B 5 -62.5 67.5 -57.5 72.5 {name=gnd dir=inout}
A 4 0 -10 60 270 180 {}
P 4 5 0 -70 -130 -70 -130 50 0 50 0 50 {}
T {@symname} -78.5 -16 0 0 0.3 0.3 {}
T {@name} 105 -62 0 0 0.2 0.2 {}
T {vdd} -64 -65 3 1 0.2 0.2 {}
T {Vo} 55 -14 0 1 0.2 0.2 {}
T {B} -125 16 0 0 0.2 0.2 {}
T {A} -125 -44 0 0 0.2 0.2 {}
T {gnd} -56 45 1 1 0.2 0.2 {}

121
modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/nand_gate/testbench/nand_tb.sch Normal file
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v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 895 20 1695 420 {flags=graph
y1=-0.02
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=4e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
hcursor1_y=1.0065781
color=4
node=vo}
B 2 1715 20 2515 420 {flags=graph
y1=0
y2=1
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=4e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
hcursor1_y=1.0065781
color=4
node=a}
B 2 1715 440 2515 840 {flags=graph
y1=0
y2=1
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=4e-06
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
hcursor1_y=1.0065781
color=7
node=b}
N 140 320 140 340 {lab=A}
N 140 380 140 410 {lab=GND}
N 90 320 90 340 {lab=vdd}
N 90 400 90 410 {lab=GND}
N 140 440 140 460 {lab=B}
N 140 500 140 530 {lab=GND}
N 550 340 570 340 {lab=A}
N 550 400 570 400 {lab=B}
N 660 260 660 290 {lab=vdd}
N 660 450 660 470 {lab=GND}
N 810 370 820 370 {lab=Vo}
N 810 370 810 390 {lab=Vo}
N 800 370 810 370 {lab=Vo}
N 810 450 810 470 {lab=GND}
N 660 470 810 470 {lab=GND}
C {devices/code_shown.sym} 55 80 0 0 {name=NGSPICE only_toplevel=true
value="
.control
tran 1u 4u
write nand_tb.raw
.endc
"}
C {devices/code_shown.sym} 65 215 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value=".lib cornerMOSlv.lib mos_tt
"}
C {devices/lab_pin.sym} 140 320 2 0 {name=p24 sig_type=std_logic lab=A}
C {devices/gnd.sym} 140 410 0 0 {name=l6 lab=GND}
C {devices/vsource.sym} 140 370 0 0 {name=V1 value="dc 0 ac 0 PULSE(0 1 0 1n 1n 2u 4u)"}
C {devices/vsource.sym} 90 370 0 1 {name=V6 value=1.2}
C {devices/gnd.sym} 90 410 0 1 {name=l11 lab=GND
value=1.2}
C {devices/lab_pin.sym} 90 320 2 1 {name=p26 sig_type=std_logic lab=vdd}
C {devices/launcher.sym} 962.5 460 0 0 {name=h1
descr="load waves Ctrl + left click"
tclcommand="xschem raw_read $netlist_dir/nand_tb.raw tran"
}
C {devices/lab_pin.sym} 140 440 2 0 {name=p1 sig_type=std_logic lab=B}
C {devices/gnd.sym} 140 530 0 0 {name=l1 lab=GND}
C {devices/vsource.sym} 140 490 0 0 {name=V2 value="dc 0 ac 0 PULSE(0 1 0 1n 1n 1u 2u)"}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/nand_gate/schematic/nand_gate.sym} 720 380 0 0 {name=x1}
C {devices/lab_pin.sym} 550 340 2 1 {name=p2 sig_type=std_logic lab=A}
C {devices/lab_pin.sym} 550 400 2 1 {name=p3 sig_type=std_logic lab=B}
C {devices/lab_pin.sym} 660 260 2 1 {name=p4 sig_type=std_logic lab=vdd}
C {devices/gnd.sym} 660 470 0 1 {name=l2 lab=GND
value=1.2}
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C {lab_pin.sym} 1470 -880 0 0 {name=p66 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1470 -790 0 0 {name=p67 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1470 -740 0 0 {name=p68 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 300 -440 0 0 {name=p69 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 300 -250 0 0 {name=p70 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 300 -160 0 0 {name=p71 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 300 -110 0 0 {name=p72 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 900 -450 0 0 {name=p73 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 900 -260 0 0 {name=p74 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 900 -170 0 0 {name=p75 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 900 -120 0 0 {name=p76 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1480 -460 0 0 {name=p77 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1480 -180 0 0 {name=p78 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1480 -130 0 0 {name=p79 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 1480 -270 0 0 {name=p80 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 2050 -470 0 0 {name=p81 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 2050 -280 0 0 {name=p82 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 2050 -190 0 0 {name=p83 sig_type=std_logic lab=gnd}
C {lab_pin.sym} 2050 -140 0 0 {name=p84 sig_type=std_logic lab=gnd}

66
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@ -0,0 +1,66 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -140 -40 -140 40 {}
L 4 -140 40 140 40 {}
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L 7 40 -60 40 -40 {}
L 7 90 40 90 60 {}
L 7 60 40 60 60 {}
L 7 10 -60 10 -40 {}
L 7 30 40 30 60 {}
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L 7 0 40 0 60 {}
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B 5 -52.5 -62.5 -47.5 -57.5 {name=S5 dir=inout}
B 5 -82.5 -62.5 -77.5 -57.5 {name=S6 dir=inout}
B 5 -32.5 57.5 -27.5 62.5 {name=D5 dir=inout}
B 5 -62.5 57.5 -57.5 62.5 {name=D6 dir=inout}
B 5 -112.5 -62.5 -107.5 -57.5 {name=S_MSB dir=inout}
B 5 -102.5 57.5 -97.5 62.5 {name=D_MSB dir=inout}
B 5 67.5 -62.5 72.5 -57.5 {name=S1 dir=inout}
B 5 37.5 -62.5 42.5 -57.5 {name=S2 dir=inout}
B 5 87.5 57.5 92.5 62.5 {name=D1 dir=inout}
B 5 57.5 57.5 62.5 62.5 {name=D2 dir=inout}
B 5 7.5 -62.5 12.5 -57.5 {name=S3 dir=inout}
B 5 27.5 57.5 32.5 62.5 {name=D3 dir=inout}
B 5 -22.5 -62.5 -17.5 -57.5 {name=S4 dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=D4 dir=inout}
T {@symname} -112 -6 0 0 0.3 0.3 {}
T {@name} 75 -2 0 0 0.2 0.2 {}
T {vref} 115 -34 0 1 0.2 0.2 {}
T {vdd} 120 34 2 1 0.2 0.2 {}
T {gnd} 97.5 34 2 1 0.2 0.2 {}
T {S5} -45 -34 0 1 0.2 0.2 {}
T {S6} -75 -34 0 1 0.2 0.2 {}
T {D5} -35 34 2 1 0.2 0.2 {}
T {D6} -65 34 2 1 0.2 0.2 {}
T {S_MSB} -95 -34 0 1 0.2 0.2 {}
T {D_MSB} -115 34 2 1 0.2 0.2 {}
T {S1} 75 -34 0 1 0.2 0.2 {}
T {S2} 45 -34 0 1 0.2 0.2 {}
T {D1} 94 35 1 1 0.2 0.2 {}
T {D2} 64 35 1 1 0.2 0.2 {}
T {S3} 15 -34 0 1 0.2 0.2 {}
T {D3} 25 34 2 1 0.2 0.2 {}
T {S4} -15 -34 0 1 0.2 0.2 {}
T {D4} -5 34 2 1 0.2 0.2 {}

134
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@ -0,0 +1,134 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 1960 -1930 2760 -1530 {flags=graph
y1=-0.0024
y2=0.61
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1e-07
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node="1
2
3
4
5
6
7
8"
color="8 4 4 4 4 4 4 4"
dataset=-1
unitx=1
logx=0
logy=0
}
B 2 1950 -1480 2750 -1080 {flags=graph
y1=0
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1e-07
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
color=4
node=clk_comp}
N 1500 -1480 1500 -1420 {lab=vref}
N 1260 -1480 1260 -1420 {lab=1}
N 1290 -1480 1290 -1420 {lab=2}
N 1320 -1480 1320 -1420 {lab=3}
N 1350 -1480 1350 -1420 {lab=4}
N 1380 -1480 1380 -1420 {lab=5}
N 1410 -1480 1410 -1420 {lab=6}
N 1440 -1480 1440 -1420 {lab=7}
N 1470 -1480 1470 -1420 {lab=8}
N 1510 -1600 1550 -1600 {lab=vdd}
N 1490 -1620 1490 -1600 {lab=GND}
N 1490 -1620 1610 -1620 {lab=GND}
N 980 -1730 980 -1710 {lab=clk_comp}
N 980 -1670 980 -1640 {lab=GND}
N 980 -1600 980 -1580 {lab=vdd}
N 980 -1540 980 -1510 {lab=GND}
N 980 -1460 980 -1440 {lab=vref}
N 980 -1400 980 -1370 {lab=GND}
N 1440 -1730 1470 -1730 {lab=clk_comp}
N 1470 -1730 1470 -1600 {lab=clk_comp}
N 1440 -1730 1440 -1600 {lab=clk_comp}
N 1410 -1730 1440 -1730 {lab=clk_comp}
N 1410 -1730 1410 -1600 {lab=clk_comp}
N 1380 -1730 1410 -1730 {lab=clk_comp}
N 1380 -1730 1380 -1600 {lab=clk_comp}
N 1350 -1730 1380 -1730 {lab=clk_comp}
N 1350 -1730 1350 -1600 {lab=clk_comp}
N 1320 -1730 1350 -1730 {lab=clk_comp}
N 1320 -1730 1320 -1600 {lab=clk_comp}
N 1290 -1730 1320 -1730 {lab=clk_comp}
N 1290 -1730 1290 -1600 {lab=clk_comp}
N 1260 -1730 1290 -1730 {lab=clk_comp}
N 1260 -1730 1260 -1600 {lab=clk_comp}
N 980 -1730 1260 -1730 {lab=clk_comp}
N 1190 -1360 1220 -1360 {lab=vdd}
N 1540 -1360 1590 -1360 {lab=vo}
C {devices/lab_pin.sym} 1550 -1600 2 0 {name=p12 sig_type=std_logic lab=vdd}
C {devices/lab_pin.sym} 1500 -1440 2 0 {name=p8 sig_type=std_logic lab=vref}
C {switch_array.sym} 1380 -1540 2 1 {name=x5}
C {gnd.sym} 1610 -1620 0 0 {name=l1 lab=GND}
C {devices/lab_pin.sym} 1260 -1440 0 0 {name=p77 sig_type=std_logic lab=1}
C {devices/lab_pin.sym} 1290 -1440 0 0 {name=p78 sig_type=std_logic lab=2}
C {devices/lab_pin.sym} 1320 -1440 0 0 {name=p79 sig_type=std_logic lab=3}
C {devices/lab_pin.sym} 1350 -1440 0 0 {name=p80 sig_type=std_logic lab=4}
C {devices/lab_pin.sym} 1380 -1440 0 0 {name=p81 sig_type=std_logic lab=5}
C {devices/lab_pin.sym} 1410 -1440 0 0 {name=p82 sig_type=std_logic lab=6}
C {devices/lab_pin.sym} 1440 -1440 0 0 {name=p83 sig_type=std_logic lab=7}
C {devices/lab_pin.sym} 1470 -1440 0 0 {name=p84 sig_type=std_logic lab=8}
C {devices/lab_pin.sym} 980 -1730 2 0 {name=p24 sig_type=std_logic lab=clk_comp}
C {devices/gnd.sym} 980 -1640 0 0 {name=l6 lab=GND}
C {devices/vsource.sym} 980 -1680 0 0 {name=V1 value="dc 0 ac 0 PULSE(0 1.2 0 1n 1n 31.25n 62.5n)"}
C {devices/code_shown.sym} 970 -1310 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.control
tran 1n 100n
save all
write switch_array_tb.raw
.endc
"}
C {devices/lab_pin.sym} 980 -1600 2 0 {name=p1 sig_type=std_logic lab=vdd}
C {devices/gnd.sym} 980 -1510 0 0 {name=l2 lab=GND}
C {devices/lab_pin.sym} 980 -1460 2 0 {name=p2 sig_type=std_logic lab=vref}
C {devices/gnd.sym} 980 -1370 0 0 {name=l3 lab=GND}
C {devices/vsource.sym} 980 -1410 0 0 {name=V3 value=0.6}
C {launcher.sym} 2010 -1510 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/switch_array_tb.raw tran"
}
C {devices/lab_pin.sym} 980 -1600 2 0 {name=p3 sig_type=std_logic lab=vdd}
C {devices/gnd.sym} 980 -1510 0 0 {name=l4 lab=GND}
C {devices/vsource.sym} 980 -1550 0 0 {name=V4 value=1.2}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/C-DAC/C-DAC.sym} 1370 -1360 2 1 {name=x3}
C {devices/lab_pin.sym} 1590 -1360 2 0 {name=p4 sig_type=std_logic lab=vo}
C {devices/code_shown.sym} 940 -1060 0 0 {name=MODEL1 only_toplevel=true
format="tcleval( @value )"
value=".lib cornerMOSlv.lib mos_tt
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
"}
C {devices/lab_pin.sym} 1190 -1360 2 1 {name=p5 sig_type=std_logic lab=vdd}

508
modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/SAR_ADC_tb.sch Normal file
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@ -0,0 +1,508 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 2015 -1020 2815 -620 {flags=graph
y1=-0.044
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1e-05
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
color="12 7"
node="cdac_v+
cdac_v-"
hilight_wave=0
hcursor1_y=1.2502139}
B 2 2015 -1430 2815 -1030 {flags=graph
y1=-0.6
y2=0.6
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1e-05
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
dataset=-1
unitx=1
logx=0
logy=0
color=4
node=vin_diff
hcursor1_y=1.0065781}
N 345 -620 405 -620 {
lab=#net1}
N 265 -620 285 -620 {lab=clk_samp}
N 265 -640 285 -640 {lab=Om}
N 265 -660 285 -660 {lab=vdd}
N 265 -680 285 -680 {lab=Op}
N 565 -870 615 -870 {lab=#net2}
N 565 -850 615 -850 {lab=#net3}
N 565 -830 615 -830 {lab=#net4}
N 565 -810 615 -810 {lab=#net5}
N 565 -790 615 -790 {lab=#net6}
N 565 -770 615 -770 {lab=#net7}
N 565 -750 615 -750 {lab=#net8}
N 565 -730 615 -730 {lab=#net9}
N 565 -710 615 -710 {lab=#net10}
N 565 -690 615 -690 {lab=#net11}
N 565 -670 615 -670 {lab=#net12}
N 565 -650 615 -650 {lab=#net13}
N 565 -630 615 -630 {lab=#net14}
N 565 -610 615 -610 {lab=#net15}
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N 565 -570 615 -570 {lab=#net17}
N 565 -550 615 -550 {lab=#net18}
N 565 -530 615 -530 {lab=#net19}
N 565 -510 615 -510 {lab=#net20}
N 565 -490 615 -490 {lab=#net21}
N 565 -470 615 -470 {lab=#net22}
N 565 -450 615 -450 {lab=#net23}
N 1570 -1170 1620 -1170 {lab=bias}
N 1700 -1070 1700 -1030 {lab=GND}
N 1330 -1470 1370 -1470 {lab=vdd}
N 1310 -1490 1310 -1470 {lab=GND}
N 1310 -1490 1430 -1490 {lab=GND}
N 1100 -870 1100 -850 {lab=BN_MSB}
N 1140 -870 1140 -850 {lab=BN6}
N 1170 -870 1170 -850 {lab=BN5}
N 1200 -870 1200 -850 {lab=BN4}
N 1230 -870 1230 -850 {lab=BN3}
N 1260 -870 1260 -850 {lab=BN2}
N 1290 -870 1290 -850 {lab=BN1}
N 1330 -870 1370 -870 {lab=vdd}
N 1310 -870 1310 -850 {lab=GND}
N 1310 -850 1430 -850 {lab=GND}
N 1100 -1500 1100 -1470 {lab=B_MSB}
N 1140 -1500 1140 -1470 {lab=B6}
N 1170 -1500 1170 -1470 {lab=B5}
N 1200 -1500 1200 -1470 {lab=B4}
N 1230 -1500 1230 -1470 {lab=B3}
N 1260 -1500 1260 -1470 {lab=B2}
N 1290 -1500 1290 -1470 {lab=B1}
N 920 -1110 1040 -1110 {lab=#net24}
N 780 -1160 780 -1150 {lab=GND}
N 780 -1040 780 -1030 {lab=GND}
N 840 -1160 840 -1140 {lab=vdd}
N 840 -1040 840 -1020 {lab=vdd}
N 900 -1160 900 -1140 {lab=clk_samp}
N 700 -1230 750 -1230 {lab=vin_pos}
N 700 -1110 750 -1110 {lab=vin_neg}
N 1700 -1310 1700 -1270 {lab=vdd}
N 300 -1110 300 -1090 {lab=clk_comp}
N 300 -1050 300 -1020 {lab=GND}
N 260 -1110 260 -1090 {lab=vdd}
N 260 -1030 260 -1020 {lab=GND}
N 1750 -1090 1750 -1060 {lab=clk_comp}
N 260 -1240 260 -1220 {lab=bias}
N 260 -1160 260 -1150 {lab=GND}
N 900 -1040 900 -1020 {lab=clk_samp}
N 1940 -1210 1940 -1180 {lab=Op}
N 1900 -1180 1940 -1180 {lab=Op}
N 1940 -1160 1940 -1130 {lab=Om}
N 1900 -1160 1940 -1160 {lab=Om}
N 1940 -1290 1940 -1270 {lab=GND}
N 1940 -1070 1940 -1050 {lab=GND}
N 920 -1230 1040 -1230 {lab=#net25}
N 1300 -1330 1300 -1290 {lab=vdd}
N 1300 -1330 1370 -1330 {lab=vdd}
N 1300 -1350 1300 -1330 {lab=vdd}
N 1370 -1470 1370 -1330 {lab=vdd}
N 1270 -1350 1270 -1290 {lab=#net26}
N 1240 -1350 1240 -1290 {lab=#net27}
N 1210 -1350 1210 -1290 {lab=#net28}
N 1180 -1350 1180 -1290 {lab=#net29}
N 1150 -1350 1150 -1290 {lab=#net30}
N 1120 -1350 1120 -1290 {lab=#net31}
N 1090 -1350 1090 -1290 {lab=#net32}
N 1090 -1050 1090 -990 {lab=#net33}
N 1120 -1050 1120 -990 {lab=#net34}
N 1150 -1050 1150 -990 {lab=#net35}
N 1180 -1050 1180 -990 {lab=#net36}
N 1210 -1050 1210 -990 {lab=#net37}
N 1240 -1050 1240 -990 {lab=#net38}
N 1270 -1050 1270 -990 {lab=#net39}
N 1300 -1020 1300 -990 {lab=vdd}
N 1300 -1020 1370 -1020 {lab=vdd}
N 1300 -1050 1300 -1020 {lab=vdd}
N 1370 -1020 1370 -870 {lab=vdd}
N 1360 -1230 1620 -1230 {lab=CDAC_v+}
N 1360 -1110 1620 -1110 {lab=CDAC_v-}
N 1940 -1180 1950 -1180 {lab=Op}
N 1940 -1160 1950 -1160 {lab=Om}
N 300 -1240 300 -1220 {lab=clk_samp}
N 300 -1180 300 -1150 {lab=GND}
N 300 -980 300 -960 {lab=dac_clk}
N 300 -920 300 -890 {lab=GND}
N 260 -855 260 -825 {lab=vin_pos}
N 260 -765 260 -755 {lab=GND}
N 260 -900 260 -890 {lab=GND}
N 260 -980 260 -960 {lab=vin_neg}
N 260 -700 285 -700 {lab=clk_algo}
N 345 -700 405 -700 {lab=#net40}
N 345 -680 405 -680 {lab=#net41}
N 345 -660 405 -660 {lab=#net42}
N 345 -640 405 -640 {
lab=#net43}
N 675 -870 1005 -870 {
lab=B1}
N 675 -850 1005 -850 {lab=B2}
N 675 -830 1005 -830 {lab=B3}
N 675 -810 1005 -810 {lab=B4}
N 675 -790 1005 -790 {lab=B5}
N 675 -770 1005 -770 {lab=B6}
N 675 -750 1005 -750 {lab=B_MSB}
N 675 -730 1005 -730 {lab=BN1}
N 675 -710 1005 -710 {lab=BN2}
N 675 -690 1005 -690 {lab=BN3}
N 675 -670 1005 -670 {lab=BN4}
N 675 -650 1005 -650 {lab=BN5}
N 675 -630 1005 -630 {lab=BN6}
N 675 -610 1005 -610 {lab=BN_MSB}
N 675 -590 1005 -590 {lab=D7}
N 675 -570 1005 -570 {lab=D6}
N 675 -550 1005 -550 {lab=D5}
N 675 -530 1005 -530 {lab=D4}
N 675 -510 1005 -510 {lab=D3}
N 675 -490 1005 -490 {lab=D2}
N 675 -470 1005 -470 {lab=D1}
N 675 -450 1005 -450 {lab=D0}
N 1560 -1490 1580 -1490 {lab=Op}
N 1560 -1430 1580 -1430 {lab=Om}
N 1670 -1570 1670 -1540 {lab=vdd}
N 1670 -1380 1670 -1360 {lab=GND}
N 1820 -1460 1830 -1460 {lab=clk_algo}
N 1820 -1460 1820 -1440 {lab=clk_algo}
N 1810 -1460 1820 -1460 {lab=clk_algo}
N 1820 -1380 1820 -1360 {lab=GND}
N 1670 -1360 1820 -1360 {lab=GND}
C {devices/code_shown.sym} 205 -1710 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.param T = 1u
.param T_half = T/2
.param T_algo = T/16
.param T_algo_delay = T/10
.param T_algo_PW = T/32
.param DAC_delay = 0.99*T
.param DAC_PW = T/20
.param comparator_delay = 0.328*T
.control
tran 1u 320u
let vin_diff = v(Vin_pos) - v(Vin_neg)
let comp_diff = v(op)- v(om)
set wr_singlescale
set wr_vecnames
wrdata bit_data.txt D0 D1 D2 D3 D4 D5 D6 D7 vin_diff dac_clk
write SAR_ADC_tb.raw
.endc
"}
C {devices/launcher.sym} 2072.5 -590 0 0 {name=h1
descr="load waves Ctrl + left click"
tclcommand="xschem raw_read $netlist_dir/SAR_ADC_tb.raw tran"
}
C {devices/lab_pin.sym} 300 -1240 2 0 {name=p10 sig_type=std_logic lab=clk_samp}
C {devices/lab_pin.sym} 265 -620 2 1 {name=p2 sig_type=std_logic lab=clk_samp}
C {devices/lab_pin.sym} 1370 -1470 2 0 {name=p12 sig_type=std_logic lab=vdd}
C {devices/lab_pin.sym} 265 -680 2 1 {name=p3 sig_type=std_logic lab=Op}
C {devices/lab_pin.sym} 265 -660 2 1 {name=p13 sig_type=std_logic lab=vdd}
C {devices/lab_pin.sym} 265 -640 2 1 {name=p14 sig_type=std_logic lab=Om}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -700 0 0 {name=A1
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -680 0 0 {name=A2
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -660 0 0 {name=A3
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -640 0 0 {name=A4
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -620 0 0 {name=A5
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=0.8
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -870 0 0 {name=A7
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -850 0 0 {name=A8
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -830 0 0 {name=A9
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -810 0 0 {name=A10
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -790 0 0 {name=A11
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -770 0 0 {name=A12
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -750 0 0 {name=A13
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -730 0 0 {name=A14
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -710 0 0 {name=A15
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -690 0 0 {name=A16
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -670 0 0 {name=A17
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -650 0 0 {name=A18
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -630 0 0 {name=A19
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -610 0 0 {name=A20
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -590 0 0 {name=A21
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -570 0 0 {name=A22
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -550 0 0 {name=A23
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -530 0 0 {name=A24
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -510 0 0 {name=A25
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -490 0 0 {name=A26
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -470 0 0 {name=A27
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -450 0 0 {name=A28
dac=dac1
dac_bridge_model=dac_bridge
out_low=0
out_high=1.2
}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 1770 -1170 0 0 {name=x1}
C {devices/lab_pin.sym} 1950 -1180 2 0 {name=p36 sig_type=std_logic lab=Op}
C {devices/lab_pin.sym} 1950 -1160 2 0 {name=p37 sig_type=std_logic lab=Om}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/C-DAC/C-DAC.sym} 1190 -1110 0 0 {name=x2}
C {devices/lab_pin.sym} 1570 -1170 2 1 {name=p5 sig_type=std_logic lab=bias}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array.sym} 1200 -930 0 0 {name=x4}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array.sym} 1200 -1410 2 1 {name=x5}
C {gnd.sym} 1430 -1490 0 0 {name=l1 lab=GND}
C {devices/lab_pin.sym} 1370 -870 0 1 {name=p38 sig_type=std_logic lab=vdd}
C {gnd.sym} 1430 -850 2 1 {name=l2 lab=GND}
C {devices/lab_pin.sym} 1100 -1500 1 0 {name=p40 sig_type=std_logic lab=B_MSB}
C {devices/lab_pin.sym} 1170 -1500 1 0 {name=p41 sig_type=std_logic lab=B5}
C {devices/lab_pin.sym} 1260 -1500 1 0 {name=p42 sig_type=std_logic lab=B2}
C {devices/lab_pin.sym} 1230 -1500 1 0 {name=p43 sig_type=std_logic lab=B3}
C {devices/lab_pin.sym} 1200 -1500 1 0 {name=p44 sig_type=std_logic lab=B4}
C {devices/lab_pin.sym} 1290 -1500 1 0 {name=p46 sig_type=std_logic lab=B1}
C {devices/lab_pin.sym} 1140 -1500 1 0 {name=p45 sig_type=std_logic lab=B6}
C {devices/lab_pin.sym} 1100 -850 1 1 {name=p48 sig_type=std_logic lab=BN_MSB}
C {devices/lab_pin.sym} 1170 -850 1 1 {name=p49 sig_type=std_logic lab=BN5}
C {devices/lab_pin.sym} 1260 -850 1 1 {name=p50 sig_type=std_logic lab=BN2}
C {devices/lab_pin.sym} 1230 -850 1 1 {name=p51 sig_type=std_logic lab=BN3}
C {devices/lab_pin.sym} 1200 -850 1 1 {name=p52 sig_type=std_logic lab=BN4}
C {devices/lab_pin.sym} 1290 -850 1 1 {name=p53 sig_type=std_logic lab=BN1}
C {devices/lab_pin.sym} 1140 -850 1 1 {name=p54 sig_type=std_logic lab=BN6}
C {devices/lab_pin.sym} 1005 -770 0 1 {name=p55 sig_type=std_logic lab=B6}
C {devices/lab_pin.sym} 1005 -750 0 1 {name=p56 sig_type=std_logic lab=B_MSB}
C {devices/lab_pin.sym} 1005 -810 0 1 {name=p57 sig_type=std_logic lab=B4}
C {devices/lab_pin.sym} 1005 -870 0 1 {name=p58 sig_type=std_logic lab=B1}
C {devices/lab_pin.sym} 1005 -850 0 1 {name=p59 sig_type=std_logic lab=B2}
C {devices/lab_pin.sym} 1005 -830 0 1 {name=p60 sig_type=std_logic lab=B3}
C {devices/lab_pin.sym} 1005 -790 0 1 {name=p62 sig_type=std_logic lab=B5}
C {devices/lab_pin.sym} 1005 -610 0 1 {name=p1 sig_type=std_logic lab=BN_MSB}
C {devices/lab_pin.sym} 1005 -650 0 1 {name=p6 sig_type=std_logic lab=BN5}
C {devices/lab_pin.sym} 1005 -710 0 1 {name=p7 sig_type=std_logic lab=BN2}
C {devices/lab_pin.sym} 1005 -690 0 1 {name=p15 sig_type=std_logic lab=BN3}
C {devices/lab_pin.sym} 1005 -670 0 1 {name=p16 sig_type=std_logic lab=BN4}
C {devices/lab_pin.sym} 1005 -730 0 1 {name=p18 sig_type=std_logic lab=BN1}
C {devices/lab_pin.sym} 1005 -630 0 1 {name=p19 sig_type=std_logic lab=BN6}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sym} 820 -1230 0 0 {name=x6}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sym} 820 -1110 0 0 {name=x7}
C {gnd.sym} 780 -1150 0 1 {name=l3 lab=GND}
C {gnd.sym} 780 -1030 0 1 {name=l4 lab=GND}
C {devices/lab_pin.sym} 840 -1140 2 0 {name=p20 sig_type=std_logic lab=vdd}
C {devices/lab_pin.sym} 300 -1110 2 0 {name=p24 sig_type=std_logic lab=clk_comp}
C {devices/gnd.sym} 300 -1020 0 0 {name=l6 lab=GND}
C {devices/vsource.sym} 300 -1060 0 0 {name=V1 value="dc 0 ac 0 PULSE(0 1.2 comparator_delay 10p 10p T_algo_PW T_algo)"}
C {devices/vsource.sym} 260 -1060 0 1 {name=V6 value=1.2}
C {devices/gnd.sym} 260 -1020 0 1 {name=l11 lab=GND
value=1.2}
C {devices/lab_pin.sym} 260 -1110 2 1 {name=p26 sig_type=std_logic lab=vdd}
C {devices/lab_pin.sym} 1700 -1310 2 0 {name=p65 sig_type=std_logic lab=vdd}
C {gnd.sym} 1700 -1030 0 1 {name=l12 lab=GND}
C {devices/lab_pin.sym} 1750 -1060 2 0 {name=p66 sig_type=std_logic lab=clk_comp}
C {iopin.sym} 1005 -570 0 0 {name=p67 lab=D6}
C {iopin.sym} 1005 -550 0 0 {name=p28 lab=D5}
C {iopin.sym} 1005 -530 0 0 {name=p29 lab=D4}
C {iopin.sym} 1005 -510 0 0 {name=p30 lab=D3}
C {iopin.sym} 1005 -490 0 0 {name=p31 lab=D2}
C {iopin.sym} 1005 -470 0 0 {name=p32 lab=D1}
C {iopin.sym} 1005 -450 0 0 {name=p33 lab=D0}
C {devices/code_shown.sym} 225 -1315 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value=".lib cornerMOSlv.lib mos_tt
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
"}
C {devices/vsource.sym} 260 -1190 0 1 {name=V7 value=0.6}
C {devices/gnd.sym} 260 -1150 0 1 {name=l13 lab=GND
value=1.2}
C {devices/lab_pin.sym} 260 -1240 2 1 {name=p68 sig_type=std_logic lab=bias}
C {devices/lab_pin.sym} 900 -1140 2 0 {name=p22 sig_type=std_logic lab=clk_samp}
C {devices/lab_pin.sym} 840 -1020 2 0 {name=p21 sig_type=std_logic lab=vdd}
C {devices/lab_pin.sym} 900 -1020 2 0 {name=p23 sig_type=std_logic lab=clk_samp}
C {capa.sym} 1940 -1240 2 0 {name=C1
m=1
value=50f
footprint=1206
device="ceramic capacitor"}
C {capa.sym} 1940 -1100 0 0 {name=C2
m=1
value=50f
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 1940 -1050 0 1 {name=l5 lab=GND}
C {gnd.sym} 1940 -1290 2 1 {name=l14 lab=GND}
C {devices/lab_pin.sym} 1400 -1230 3 1 {name=p74 sig_type=std_logic lab=CDAC_v+}
C {devices/lab_pin.sym} 1400 -1110 1 1 {name=p73 sig_type=std_logic lab=CDAC_v-}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/C-DAC/C-DAC.sym} 1190 -1230 2 1 {name=x3}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/sar_logic.sym} 485 -660 0 0 {name=adut1
dut=dut
d_cosim_model= d_cosim
model=./sar_logic.so}
C {devices/lab_pin.sym} 700 -1230 2 1 {name=p25 sig_type=std_logic lab=vin_pos}
C {devices/lab_pin.sym} 700 -1110 2 1 {name=p69 sig_type=std_logic lab=vin_neg}
C {devices/lab_pin.sym} 260 -855 2 1 {name=p75 sig_type=std_logic lab=vin_pos}
C {iopin.sym} 1005 -590 0 0 {name=p4 lab=D7}
C {devices/gnd.sym} 300 -1150 0 0 {name=l9 lab=GND}
C {devices/gnd.sym} 300 -890 0 0 {name=l18 lab=GND}
C {devices/vsource.sym} 300 -930 0 0 {name=V12 value="dc 0 ac 0 PULSE(0 1.2 DAC_delay 10p 10p DAC_PW T)"}
C {iopin.sym} 300 -980 0 0 {name=p17 lab=dac_clk
}
C {devices/gnd.sym} 260 -755 0 1 {name=l19 lab=GND}
C {devices/gnd.sym} 260 -890 0 1 {name=l20 lab=GND}
C {devices/vsource.sym} 260 -795 0 1 {name=V11 value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {devices/vsource.sym} 260 -930 0 1 {name=V4 value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 180)"}
C {devices/lab_pin.sym} 260 -700 2 1 {name=p27 sig_type=std_logic lab=clk_algo}
C {devices/lab_pin.sym} 260 -980 2 1 {name=p8 sig_type=std_logic lab=vin_neg}
C {devices/vsource.sym} 300 -1190 0 0 {name=V5 value="dc 0 ac 0 PULSE(0 1.2 0 10p 10p T_half T)"}
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/nand_gate/schematic/nand_gate.sym} 1730 -1450 0 0 {name=x8}
C {devices/lab_pin.sym} 1560 -1490 2 1 {name=p9 sig_type=std_logic lab=Op}
C {devices/lab_pin.sym} 1560 -1430 2 1 {name=p11 sig_type=std_logic lab=Om}
C {devices/lab_pin.sym} 1670 -1570 2 1 {name=p34 sig_type=std_logic lab=vdd}
C {devices/gnd.sym} 1670 -1360 0 1 {name=l7 lab=GND
value=1.2}
C {capa.sym} 1820 -1410 0 0 {name=C3
m=1
value=20f
footprint=1206
device="ceramic capacitor"}
C {devices/lab_pin.sym} 1830 -1460 2 0 {name=p35 sig_type=std_logic lab=clk_algo}

458
modules/module_3_8_bit_SAR_ADC/part_4_SAR_ADC/scripting/plot_adc.ipynb Normal file
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File diff suppressed because one or more lines are too long

43
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/adc_bridge1.sym
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@ -1,43 +0,0 @@
v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@s ] [ @@d ] @adc \
.model @adc @adc_bridge_model in_low=@in_low in_high=@in_high"
template="name=A1
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
"
}
V {}
S {}
E {}
L 4 -30 0 30 0 {}
L 4 -10 -5 10 0 {}
L 4 -10 5 10 0 {}
B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire propag=1}
B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire propag=0}
T {@name} -25 -10 0 0 0.12 0.12 {}
T {@adc_bridge_model} 0 -10 0 0 0.12 0.12 {}

87
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/control.sym
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@ -1,87 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@clk @@rst @@sck @@mosi @@ss ] [ @@miso @@dout_p0 @@dout_p1 @@dout_p2 @@dout_p3 @@dout_p4 @@dout_p5 @@dout_p6 @@dout_p7 @@dout_n0 @@dout_n1 @@dout_n2 @@dout_n3 @@dout_n4 @@dout_n5 @@dout_n6 @@dout_n7 ] null @dut
.model @dut @d_cosim_model simulation=@model"
template="name=adut
dut=dut
d_cosim_model= d_cosim
model=./control.so
"
}
V {}
S {}
E {}
L 4 50 -180 50 170 {}
L 4 -50 -40 -50 170 {}
L 4 -50 170 50 170 {}
L 4 -50 -180 -50 -40 {}
L 4 -50 -180 50 -180 {}
B 5 -52.5 -42.5 -47.5 -37.5 {name=clk dir=in verilog_type=wire propag=0}
B 5 -52.5 -22.5 -47.5 -17.5 {name=rst dir=in verilog_type=wire propag=0}
B 5 -52.5 -2.5 -47.5 2.5 {name=sck dir=in verilog_type=wire propag=0}
B 5 -52.5 17.5 -47.5 22.5 {name=mosi dir=in verilog_type=wire propag=0}
B 5 -52.5 37.5 -47.5 42.5 {name=ss dir=in verilog_type=wire propag=0}
B 5 47.5 -162.5 52.5 -157.5 {name=miso dir=out verilog_type=wire propag=1}
B 5 47.5 -142.5 52.5 -137.5 {name=dout_p0 dir=out verilog_type=wire propag=1}
B 5 47.5 -122.5 52.5 -117.5 {name=dout_p1 dir=out verilog_type=wire propag=1}
B 5 47.5 -102.5 52.5 -97.5 {name=dout_p2 dir=out verilog_type=wire propag=1}
B 5 47.5 -82.5 52.5 -77.5 {name=dout_p3 dir=out verilog_type=wire propag=1}
B 5 47.5 -62.5 52.5 -57.5 {name=dout_p4 dir=out verilog_type=wire propag=1}
B 5 47.5 -42.5 52.5 -37.5 {name=dout_p5 dir=out verilog_type=wire propag=1}
B 5 47.5 -22.5 52.5 -17.5 {name=dout_p6 dir=out verilog_type=wire propag=1}
B 5 47.5 -2.5 52.5 2.5 {name=dout_p7 dir=out verilog_type=wire propag=1}
B 5 47.5 17.5 52.5 22.5 {name=dout_n0 dir=out verilog_type=wire propag=1}
B 5 47.5 37.5 52.5 42.5 {name=dout_n1 dir=out verilog_type=wire propag=1}
B 5 47.5 57.5 52.5 62.5 {name=dout_n2 dir=out verilog_type=wire propag=1}
B 5 47.5 77.5 52.5 82.5 {name=dout_n3 dir=out verilog_type=wire propag=1}
B 5 47.5 97.5 52.5 102.5 {name=dout_n4 dir=out verilog_type=wire propag=1}
B 5 47.5 117.5 52.5 122.5 {name=dout_n5 dir=out verilog_type=wire propag=1}
B 5 47.5 137.5 52.5 142.5 {name=dout_n6 dir=out verilog_type=wire propag=1}
B 5 47.5 157.5 52.5 162.5 {name=dout_n7 dir=out verilog_type=wire propag=1}
T {@name} -45 -190 0 0 0.12 0.12 {}
T {@d_cosim_model} -10 -190 0 0 0.12 0.12 {}
T {clk} -40 -45 0 0 0.12 0.12 {}
T {rst} -40 -25 0 0 0.12 0.12 {}
T {sck} -40 -5 0 0 0.12 0.12 {}
T {mosi} -40 15 0 0 0.12 0.12 {}
T {ss} -40 35 0 0 0.12 0.12 {}
T {miso} 20 -165 0 0 0.12 0.12 {}
T {dout_p0} 20 -145 0 0 0.12 0.12 {}
T {dout_p1} 20 -125 0 0 0.12 0.12 {}
T {dout_p2} 20 -105 0 0 0.12 0.12 {}
T {dout_p3} 20 -85 0 0 0.12 0.12 {}
T {dout_p4} 20 -65 0 0 0.12 0.12 {}
T {dout_p5} 20 -45 0 0 0.12 0.12 {}
T {dout_p6} 20 -25 0 0 0.12 0.12 {}
T {dout_p7} 20 -5 0 0 0.12 0.12 {}
T {dout_n0} 20 15 0 0 0.12 0.12 {}
T {dout_n1} 20 35 0 0 0.12 0.12 {}
T {dout_n2} 20 55 0 0 0.12 0.12 {}
T {dout_n3} 20 75 0 0 0.12 0.12 {}
T {dout_n4} 20 95 0 0 0.12 0.12 {}
T {dout_n5} 20 115 0 0 0.12 0.12 {}
T {dout_n6} 20 135 0 0 0.12 0.12 {}
T {dout_n7} 20 155 0 0 0.12 0.12 {}

45
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/d_osc.sym
View File

@ -1,45 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name @@c2 @@c1 @clk
.model @clk @d_osc_model cntl_array=[-1 1] \
+ freq_array=[ @freq @freq ]"
template="name=aclock
clk=clk
d_osc_model=d_osc
freq=1Meg
"
}
V {}
S {}
E {}
L 4 20 -20 20 20 {}
L 4 -20 -20 -20 20 {}
L 4 -20 20 20 20 {}
L 4 -20 -20 20 -20 {}
B 5 -2.5 17.5 2.5 22.5 {name=c2 dir=out}
B 5 -2.5 -22.5 2.5 -17.5 {name=c1 dir=out}
T {@name} 25 -10 0 0 0.12 0.12 {}
T {@d_osc_model} 20 0 0 0 0.12 0.12 {}

44
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/dac_bridge1.sym
View File

@ -1,44 +0,0 @@
v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@s ] [ @@d ] @dac \
.model @dac @dac_bridge_model out_low=@out_low out_high=@out_high"
template="name=A1
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
"
}
V {}
S {}
E {}
L 4 -30 0 30 0 {}
L 4 -10 -5 10 0 {}
L 4 -10 5 10 0 {}
B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire propag=1}
B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire propag=0}
T {@name} -25 -10 0 0 0.12 0.12 {}
T {@dac_bridge_model} 0 -10 0 0 0.12 0.12 {}

87
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/decoder.sym
View File

@ -1,87 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@clk @@rst @@ctrl_1 @@ctrl_2 @@ctrl_3 @@ctrl_4 ] [ @@dout_p0 @@dout_p1 @@dout_p2 @@dout_p3 @@dout_p4 @@dout_p5 @@dout_p6 @@dout_p7 @@dout_n0 @@dout_n1 @@dout_n2 @@dout_n3 @@dout_n4 @@dout_n5 @@dout_n6 @@dout_n7 ] null @dut
.model @dut @d_cosim_model simulation=@model"
template="name=adut
dut=dut
d_cosim_model=d_cosim
model=./decoder.so
"
}
V {}
S {}
E {}
L 4 -50 -40 -50 170 {}
L 4 -50 170 50 170 {}
L 4 -50 -150 50 -150 {}
L 4 -50 -150 -50 -40 {}
L 4 50 -150 50 170 {}
B 5 -52.5 -32.5 -47.5 -27.5 {name=ctrl_1 dir=in verilog_type=wire propag=0}
B 5 -52.5 -12.5 -47.5 -7.5 {name=ctrl_2 dir=in verilog_type=wire propag=0}
B 5 -52.5 7.5 -47.5 12.5 {name=ctrl_3 dir=in verilog_type=wire propag=0}
B 5 -52.5 27.5 -47.5 32.5 {name=ctrl_4 dir=in verilog_type=wire propag=0}
B 5 47.5 -142.5 52.5 -137.5 {name=dout_p0 dir=out verilog_type=wire propag=1}
B 5 47.5 -122.5 52.5 -117.5 {name=dout_p1 dir=out verilog_type=wire propag=1}
B 5 47.5 -102.5 52.5 -97.5 {name=dout_p2 dir=out verilog_type=wire propag=1}
B 5 47.5 -82.5 52.5 -77.5 {name=dout_p3 dir=out verilog_type=wire propag=1}
B 5 47.5 -62.5 52.5 -57.5 {name=dout_p4 dir=out verilog_type=wire propag=1}
B 5 47.5 -42.5 52.5 -37.5 {name=dout_p5 dir=out verilog_type=wire propag=1}
B 5 47.5 -22.5 52.5 -17.5 {name=dout_p6 dir=out verilog_type=wire propag=1}
B 5 47.5 -2.5 52.5 2.5 {name=dout_p7 dir=out verilog_type=wire propag=1}
B 5 47.5 17.5 52.5 22.5 {name=dout_n0 dir=out verilog_type=wire propag=1}
B 5 47.5 37.5 52.5 42.5 {name=dout_n1 dir=out verilog_type=wire propag=1}
B 5 47.5 57.5 52.5 62.5 {name=dout_n2 dir=out verilog_type=wire propag=1}
B 5 47.5 77.5 52.5 82.5 {name=dout_n3 dir=out verilog_type=wire propag=1}
B 5 47.5 97.5 52.5 102.5 {name=dout_n4 dir=out verilog_type=wire propag=1}
B 5 47.5 117.5 52.5 122.5 {name=dout_n5 dir=out verilog_type=wire propag=1}
B 5 47.5 137.5 52.5 142.5 {name=dout_n6 dir=out verilog_type=wire propag=1}
B 5 47.5 157.5 52.5 162.5 {name=dout_n7 dir=out verilog_type=wire propag=1}
B 5 -52.5 47.5 -47.5 52.5 {name=clk dir=in verilog_type=wire propag=0}
B 5 -52.5 67.5 -47.5 72.5 {name=rst dir=in verilog_type=wire propag=0}
T {@name} -45 -160 0 0 0.12 0.12 {}
T {@d_cosim_model} -10 -160 0 0 0.12 0.12 {}
T {ctrl_1} -40 -35 0 0 0.12 0.12 {}
T {dout_p0} 20 -145 0 0 0.12 0.12 {}
T {dout_p1} 20 -125 0 0 0.12 0.12 {}
T {dout_p2} 20 -105 0 0 0.12 0.12 {}
T {dout_p3} 20 -85 0 0 0.12 0.12 {}
T {dout_p4} 20 -65 0 0 0.12 0.12 {}
T {dout_p5} 20 -45 0 0 0.12 0.12 {}
T {dout_p6} 20 -25 0 0 0.12 0.12 {}
T {dout_p7} 20 -5 0 0 0.12 0.12 {}
T {dout_n0} 20 15 0 0 0.12 0.12 {}
T {dout_n1} 20 35 0 0 0.12 0.12 {}
T {dout_n2} 20 55 0 0 0.12 0.12 {}
T {dout_n3} 20 75 0 0 0.12 0.12 {}
T {dout_n4} 20 95 0 0 0.12 0.12 {}
T {dout_n5} 20 115 0 0 0.12 0.12 {}
T {dout_n6} 20 135 0 0 0.12 0.12 {}
T {dout_n7} 20 155 0 0 0.12 0.12 {}
T {ctrl_2} -40 -15 0 0 0.12 0.12 {}
T {ctrl_3} -40 5 0 0 0.12 0.12 {}
T {ctrl_4} -40 25 0 0 0.12 0.12 {}
T {clk} -40 45 0 0 0.12 0.12 {}
T {rst} -40 65 0 0 0.12 0.12 {}

48
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/filesource.sym
View File

@ -1,48 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [@@c1 @@c2] @filesrc
.model @filesrc @filesrc_model (file=\"@file\" \
+ amploffset=[0.0 0.0] amplscale=[1.0 1.0] \
+ timeoffset=0 timescale=1 \
+ timerelative=false amplstep=false)"
template="name=afsrc
file=sck.txt
filesrc=filesrc
filesrc_model=filesource
"
}
V {}
S {}
E {}
L 4 20 -20 20 20 {}
L 4 -20 -20 -20 20 {}
L 4 -20 20 20 20 {}
L 4 -20 -20 20 -20 {}
B 5 -2.5 17.5 2.5 22.5 {name=c2 dir=out}
B 5 -2.5 -22.5 2.5 -17.5 {name=c1 dir=out}
T {@name} 25 -10 0 0 0.12 0.12 {}
T {@d_osc_model} 20 0 0 0 0.12 0.12 {}

222
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/multiplexer.sch
View File

@ -1,222 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N 300 -150 340 -150 {
lab=en1_n}
N 300 -130 340 -130 {
lab=en1_p}
N 300 -180 340 -180 {
lab=IO1}
N 640 -180 680 -180 {
lab=Mout}
N 490 -100 490 -80 {
lab=Vss}
N 490 -240 490 -220 {
lab=Vdd}
N 300 -360 340 -360 {
lab=en2_n}
N 300 -340 340 -340 {
lab=en2_p}
N 300 -390 340 -390 {
lab=IO2}
N 640 -390 680 -390 {
lab=Mout}
N 490 -310 490 -290 {
lab=Vss}
N 490 -450 490 -430 {
lab=Vdd}
N 300 -570 340 -570 {
lab=en3_n}
N 300 -550 340 -550 {
lab=en3_p}
N 300 -600 340 -600 {
lab=IO3}
N 640 -600 680 -600 {
lab=Mout}
N 490 -520 490 -500 {
lab=Vss}
N 490 -660 490 -640 {
lab=Vdd}
N 300 -780 340 -780 {
lab=en4_n}
N 300 -760 340 -760 {
lab=en4_p}
N 300 -810 340 -810 {
lab=IO4}
N 640 -810 680 -810 {
lab=Mout}
N 490 -730 490 -710 {
lab=Vss}
N 300 -990 340 -990 {
lab=en5_n}
N 300 -970 340 -970 {
lab=en5_p}
N 300 -1020 340 -1020 {
lab=IO5}
N 640 -1020 680 -1020 {
lab=Mout}
N 490 -940 490 -920 {
lab=Vss}
N 490 -1080 490 -1060 {
lab=Vdd}
N 300 -1200 340 -1200 {
lab=en6_n}
N 300 -1180 340 -1180 {
lab=en6_p}
N 300 -1230 340 -1230 {
lab=IO6}
N 640 -1230 680 -1230 {
lab=Mout}
N 490 -1150 490 -1130 {
lab=Vss}
N 490 -1290 490 -1270 {
lab=Vdd}
N 300 -1410 340 -1410 {
lab=en7_n}
N 300 -1390 340 -1390 {
lab=en7_p}
N 300 -1440 340 -1440 {
lab=IO7}
N 640 -1440 680 -1440 {
lab=Mout}
N 490 -1360 490 -1340 {
lab=Vss}
N 490 -1500 490 -1480 {
lab=Vdd}
N 300 -1620 340 -1620 {
lab=en8_n}
N 300 -1600 340 -1600 {
lab=en8_p}
N 300 -1650 340 -1650 {
lab=IO8}
N 640 -1650 680 -1650 {
lab=Mout}
N 490 -1570 490 -1550 {
lab=Vss}
N 680 -390 680 -180 {
lab=Mout}
N 680 -600 680 -390 {
lab=Mout}
N 680 -810 680 -600 {
lab=Mout}
N 680 -910 680 -810 {
lab=Mout}
N 680 -1440 680 -1230 {
lab=Mout}
N 680 -1650 680 -1440 {
lab=Mout}
N 680 -910 720 -910 {
lab=Mout}
N 680 -1230 680 -1020 {
lab=Mout}
N 490 -1710 490 -1690 {
lab=Vdd}
N 150 -1710 490 -1710 {
lab=Vdd}
N 150 -1750 150 -1710 {
lab=Vdd}
N 150 -450 150 -240 {
lab=Vdd}
N 150 -240 490 -240 {
lab=Vdd}
N 110 -80 490 -80 {
lab=Vss}
N 110 -80 110 -70 {
lab=Vss}
N 110 -1550 490 -1550 {
lab=Vss}
N 110 -290 110 -80 {
lab=Vss}
N 150 -1500 490 -1500 {
lab=Vdd}
N 150 -1710 150 -1500 {
lab=Vdd}
N 110 -1340 490 -1340 {
lab=Vss}
N 110 -1550 110 -1340 {
lab=Vss}
N 150 -1290 490 -1290 {
lab=Vdd}
N 150 -1500 150 -1290 {
lab=Vdd}
N 110 -1130 490 -1130 {
lab=Vss}
N 110 -1340 110 -1130 {
lab=Vss}
N 150 -1080 490 -1080 {
lab=Vdd}
N 150 -1290 150 -1080 {
lab=Vdd}
N 110 -920 490 -920 {
lab=Vss}
N 110 -1130 110 -920 {
lab=Vss}
N 490 -870 490 -850 {
lab=Vdd}
N 150 -870 490 -870 {
lab=Vdd}
N 150 -1080 150 -870 {
lab=Vdd}
N 110 -710 490 -710 {
lab=Vss}
N 110 -920 110 -710 {
lab=Vss}
N 150 -660 490 -660 {
lab=Vdd}
N 150 -870 150 -660 {
lab=Vdd}
N 110 -500 490 -500 {
lab=Vss}
N 110 -710 110 -500 {
lab=Vss}
N 150 -450 490 -450 {
lab=Vdd}
N 150 -660 150 -450 {
lab=Vdd}
N 110 -290 490 -290 {
lab=Vss}
N 110 -500 110 -290 {
lab=Vss}
N 680 -1020 680 -910 {
lab=Mout}
C {devices/title.sym} -310 160 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
C {transmission_gate.sym} 490 -160 0 0 {name=x1}
C {devices/iopin.sym} 300 -180 2 0 {name=p1 lab=IO1}
C {devices/iopin.sym} 110 -70 1 0 {name=p4 lab=Vss}
C {devices/ipin.sym} 300 -150 0 0 {name=p5 lab=en1_n}
C {devices/ipin.sym} 300 -130 0 0 {name=p6 lab=en1_p}
C {transmission_gate.sym} 490 -370 0 0 {name=x2}
C {devices/iopin.sym} 300 -390 2 0 {name=p7 lab=IO2}
C {devices/iopin.sym} 720 -910 0 0 {name=p8 lab=Mout
}
C {devices/ipin.sym} 300 -360 0 0 {name=p11 lab=en2_n}
C {devices/ipin.sym} 300 -340 0 0 {name=p12 lab=en2_p}
C {transmission_gate.sym} 490 -580 0 0 {name=x3}
C {devices/iopin.sym} 300 -600 2 0 {name=p2 lab=IO3}
C {devices/ipin.sym} 300 -570 0 0 {name=p15 lab=en3_n}
C {devices/ipin.sym} 300 -550 0 0 {name=p16 lab=en3_p}
C {transmission_gate.sym} 490 -790 0 0 {name=x4}
C {devices/iopin.sym} 300 -810 2 0 {name=p17 lab=IO4}
C {devices/ipin.sym} 300 -780 0 0 {name=p20 lab=en4_n}
C {devices/ipin.sym} 300 -760 0 0 {name=p21 lab=en4_p}
C {transmission_gate.sym} 490 -1000 0 0 {name=x5}
C {devices/iopin.sym} 300 -1020 2 0 {name=p22 lab=IO5}
C {devices/ipin.sym} 300 -990 0 0 {name=p25 lab=en5_n}
C {devices/ipin.sym} 300 -970 0 0 {name=p26 lab=en5_p}
C {transmission_gate.sym} 490 -1210 0 0 {name=x6}
C {devices/iopin.sym} 300 -1230 2 0 {name=p27 lab=IO6}
C {devices/ipin.sym} 300 -1200 0 0 {name=p30 lab=en6_n}
C {devices/ipin.sym} 300 -1180 0 0 {name=p31 lab=en6_p}
C {transmission_gate.sym} 490 -1420 0 0 {name=x7}
C {devices/iopin.sym} 300 -1440 2 0 {name=p32 lab=IO7}
C {devices/ipin.sym} 300 -1410 0 0 {name=p35 lab=en7_n}
C {devices/ipin.sym} 300 -1390 0 0 {name=p36 lab=en7_p}
C {transmission_gate.sym} 490 -1630 0 0 {name=x8}
C {devices/iopin.sym} 300 -1650 2 0 {name=p37 lab=IO8}
C {devices/iopin.sym} 150 -1750 3 0 {name=p38 lab=Vdd}
C {devices/ipin.sym} 300 -1620 0 0 {name=p40 lab=en8_n}
C {devices/ipin.sym} 300 -1600 0 0 {name=p41 lab=en8_p}

97
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/multiplexer.sym
View File

@ -1,97 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -240 130 -240 {}
L 4 -130 240 130 240 {}
L 4 -150 -210 -130 -210 {}
L 4 -150 -190 -130 -190 {}
L 4 -150 -150 -130 -150 {}
L 4 -150 -130 -130 -130 {}
L 4 -150 -90 -130 -90 {}
L 4 -150 -70 -130 -70 {}
L 4 -150 -30 -130 -30 {}
L 4 -150 -10 -130 -10 {}
L 4 -150 30 -130 30 {}
L 4 -150 50 -130 50 {}
L 4 -150 90 -130 90 {}
L 4 -150 110 -130 110 {}
L 4 -150 150 -130 150 {}
L 4 -150 170 -130 170 {}
L 4 -150 210 -130 210 {}
L 4 -150 230 -130 230 {}
L 4 130 -240 130 240 {}
L 4 -130 -240 -130 240 {}
L 7 0 -260 0 -240 {}
L 7 -150 -230 -130 -230 {}
L 7 -150 -170 -130 -170 {}
L 7 -150 -110 -130 -110 {}
L 7 -150 -50 -130 -50 {}
L 7 130 0 150 0 {}
L 7 -150 10 -130 10 {}
L 7 -150 70 -130 70 {}
L 7 -150 130 -130 130 {}
L 7 -150 190 -130 190 {}
L 7 0 240 0 260 {}
B 5 -2.5 -262.5 2.5 -257.5 {name=Vdd dir=inout}
B 5 -152.5 -232.5 -147.5 -227.5 {name=IO8 dir=inout}
B 5 -152.5 -212.5 -147.5 -207.5 {name=en8_n dir=in}
B 5 -152.5 -192.5 -147.5 -187.5 {name=en8_p dir=in}
B 5 -152.5 -172.5 -147.5 -167.5 {name=IO7 dir=inout}
B 5 -152.5 -152.5 -147.5 -147.5 {name=en7_n dir=in}
B 5 -152.5 -132.5 -147.5 -127.5 {name=en7_p dir=in}
B 5 -152.5 -112.5 -147.5 -107.5 {name=IO6 dir=inout}
B 5 -152.5 -92.5 -147.5 -87.5 {name=en6_n dir=in}
B 5 -152.5 -72.5 -147.5 -67.5 {name=en6_p dir=in}
B 5 -152.5 -52.5 -147.5 -47.5 {name=IO5 dir=inout}
B 5 -152.5 -32.5 -147.5 -27.5 {name=en5_n dir=in}
B 5 -152.5 -12.5 -147.5 -7.5 {name=en5_p dir=in}
B 5 147.5 -2.5 152.5 2.5 {name=Mout dir=inout}
B 5 -152.5 7.5 -147.5 12.5 {name=IO4 dir=inout}
B 5 -152.5 27.5 -147.5 32.5 {name=en4_n dir=in}
B 5 -152.5 47.5 -147.5 52.5 {name=en4_p dir=in}
B 5 -152.5 67.5 -147.5 72.5 {name=IO3 dir=inout}
B 5 -152.5 87.5 -147.5 92.5 {name=en3_n dir=in}
B 5 -152.5 107.5 -147.5 112.5 {name=en3_p dir=in}
B 5 -152.5 127.5 -147.5 132.5 {name=IO2 dir=inout}
B 5 -152.5 147.5 -147.5 152.5 {name=en2_n dir=in}
B 5 -152.5 167.5 -147.5 172.5 {name=en2_p dir=in}
B 5 -152.5 187.5 -147.5 192.5 {name=IO1 dir=inout}
B 5 -152.5 207.5 -147.5 212.5 {name=en1_n dir=in}
B 5 -152.5 227.5 -147.5 232.5 {name=en1_p dir=in}
B 5 -2.5 257.5 2.5 262.5 {name=Vss dir=inout}
T {@symname} -47.5 -6 0 0 0.3 0.3 {}
T {@name} 105 -262 0 0 0.2 0.2 {}
T {Vdd} 15 -234 0 1 0.2 0.2 {}
T {IO8} -105 -234 0 1 0.2 0.2 {}
T {en8_n} -125 -214 0 0 0.2 0.2 {}
T {en8_p} -125 -194 0 0 0.2 0.2 {}
T {IO7} -105 -174 0 1 0.2 0.2 {}
T {en7_n} -125 -154 0 0 0.2 0.2 {}
T {en7_p} -125 -134 0 0 0.2 0.2 {}
T {IO6} -105 -114 0 1 0.2 0.2 {}
T {en6_n} -125 -94 0 0 0.2 0.2 {}
T {en6_p} -125 -74 0 0 0.2 0.2 {}
T {IO5} -105 -54 0 1 0.2 0.2 {}
T {en5_n} -125 -34 0 0 0.2 0.2 {}
T {en5_p} -125 -14 0 0 0.2 0.2 {}
T {Mout} 125 -4 0 1 0.2 0.2 {}
T {IO4} -105 6 0 1 0.2 0.2 {}
T {en4_n} -125 26 0 0 0.2 0.2 {}
T {en4_p} -125 46 0 0 0.2 0.2 {}
T {IO3} -105 66 0 1 0.2 0.2 {}
T {en3_n} -125 86 0 0 0.2 0.2 {}
T {en3_p} -125 106 0 0 0.2 0.2 {}
T {IO2} -105 126 0 1 0.2 0.2 {}
T {en2_n} -125 146 0 0 0.2 0.2 {}
T {en2_p} -125 166 0 0 0.2 0.2 {}
T {IO1} -105 186 0 1 0.2 0.2 {}
T {en1_n} -125 206 0 0 0.2 0.2 {}
T {en1_p} -125 226 0 0 0.2 0.2 {}
T {Vss} 15 226 0 1 0.2 0.2 {}

525
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/multiplexer_mixed_decoder_tb.sch
View File

@ -1,525 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
B 2 440 -710 1240 -310 {flags=graph
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=1.1e-16
rainbow=0
color="4 4 4 4 4 4 4 4"
node="v_in1
v_in2
v_in3
v_in4
v_in5
v_in6
v_in7
v_in8"}
B 2 440 -1140 1240 -740 {flags=graph
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0
rainbow=0
color="7 6 5 8 10 9 11 12"
node="en1_p
en2_p
en3_p
en4_p
en5_p
en6_p
en7_p
en8_p"
hilight_wave=1}
B 2 440 -290 1240 110 {flags=graph
y2=0.91
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0.29
rainbow=0
color=9
node=v_out
hilight_wave=0}
B 2 440 -1560 1240 -1160 {flags=graph
y2=0
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=-1.3
rainbow=0
hilight_wave=5
color="8 6 4 15 21"
node="ctrl_1
ctrl_2
ctrl_3
ctrl_4
rst"}
B 2 -530 -1780 270 -1380 {flags=graph
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0
rainbow=0
hilight_wave=5
color=9
node=clk
y2=3.3}
N -150 -780 -150 -760 {
lab=GND}
N 250 -110 250 -90 {
lab=V_out}
N -150 -880 -150 -840 {
lab=Vdd}
N 250 -140 250 -110 {
lab=V_out}
N 0 -380 0 -370 {
lab=#net1}
N 0 -450 0 -440 {
lab=Vdd}
N 0 150 -0 160 {
lab=GND}
N 1380 130 1380 150 {
lab=GND}
N 1380 60 1380 70 {
lab=V_in1}
N 1380 -50 1380 -30 {
lab=GND}
N 1380 -230 1380 -210 {
lab=GND}
N 1380 -410 1380 -390 {
lab=GND}
N 1380 -590 1380 -570 {
lab=GND}
N 1380 -770 1380 -750 {
lab=GND}
N 1380 -950 1380 -930 {
lab=GND}
N 1380 -1120 1380 -1100 {
lab=GND}
N -560 -140 -530 -140 {
lab=#net2}
N -560 -160 -530 -160 {
lab=#net3}
N -560 -180 -530 -180 {
lab=#net4}
N -560 -200 -530 -200 {
lab=#net5}
N 150 -110 250 -110 {
lab=V_out}
N -790 -60 -790 -10 {
lab=clk}
N -630 -60 -630 80 {
lab=rst}
N -790 30 -790 50 {
lab=GND}
N -790 -60 -770 -60 {
lab=clk}
N -790 -120 -790 -60 {
lab=clk}
N -630 -60 -610 -60 {
lab=rst}
N -630 -100 -630 -60 {
lab=rst}
N -550 -120 -530 -120 {
lab=#net6}
N -550 -100 -530 -100 {
lab=#net7}
N -790 -120 -610 -120 {
lab=clk}
N -630 -100 -610 -100 {
lab=rst}
N -740 -200 -620 -200 {
lab=ctrl_1}
N -1200 -180 -1200 -50 {
lab=ctrl_2}
N -810 -180 -620 -180 {
lab=ctrl_2}
N -880 -160 -620 -160 {
lab=ctrl_3}
N -1120 -160 -1120 20 {
lab=ctrl_3}
N -1050 -140 -1050 90 {
lab=ctrl_4}
N -960 -140 -620 -140 {
lab=ctrl_4}
N -740 -230 -740 -200 {
lab=ctrl_1}
N -1270 -200 -740 -200 {
lab=ctrl_1}
N -810 -230 -810 -180 {
lab=ctrl_2}
N -1200 -180 -810 -180 {
lab=ctrl_2}
N -880 -230 -880 -160 {
lab=ctrl_3}
N -1120 -160 -880 -160 {
lab=ctrl_3}
N -960 -230 -960 -140 {
lab=ctrl_4}
N -1050 -140 -960 -140 {
lab=ctrl_4}
N -1270 -200 -1270 -170 {
lab=ctrl_1}
N -1120 80 -1120 100 {
lab=GND}
N -1050 150 -1050 170 {
lab=GND}
N -1200 10 -1200 20 {
lab=GND}
C {devices/code_shown.sym} -440 -1050 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt\\
.lib cornerRES.lib res_typ\\
"}
C {devices/code_shown.sym} 130 -1090 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.control
save all
tran 100n 220u
write tran_decoder.raw
.endc
"}
C {devices/vsource.sym} -150 -810 0 0 {name=Vpow value=1.2}
C {devices/title.sym} -920 290 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
C {devices/launcher.sym} 530 190 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/tran_decoder.raw tran"
}
C {devices/gnd.sym} 0 160 0 0 {name=l2 lab=GND}
C {devices/ammeter.sym} 0 -410 0 0 {name=Vp}
C {devices/gnd.sym} -150 -760 0 0 {name=l1 lab=GND}
C {devices/lab_pin.sym} 250 -140 1 0 {name=p3 sig_type=std_logic lab=V_out}
C {devices/capa.sym} 250 -60 0 0 {name=C1
m=1
value=1p
footprint=1206
device="ceramic capacitor"}
C {devices/gnd.sym} 250 -30 0 0 {name=l6 lab=GND}
C {devices/lab_pin.sym} -150 -880 1 0 {name=p4 sig_type=std_logic lab=Vdd}
C {devices/lab_pin.sym} 0 -450 1 0 {name=p6 sig_type=std_logic lab=Vdd}
C {devices/lab_pin.sym} -150 80 0 0 {name=p7 sig_type=std_logic lab=V_in1}
C {devices/lab_pin.sym} -150 120 0 0 {name=p8 sig_type=std_logic lab=en1_p}
C {devices/lab_pin.sym} -150 100 0 0 {name=p9 sig_type=std_logic lab=en1_n}
C {multiplexer.sym} 0 -110 0 0 {name=x1}
C {devices/vsource.sym} 1380 100 0 0 {name=Vin2 value="dc 0 ac 1 sin(0.6, 20m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 150 0 0 {name=l11 lab=GND}
C {devices/lab_pin.sym} 1380 60 1 0 {name=p12 sig_type=std_logic lab=V_in1}
C {devices/vsource.sym} 1380 -80 0 0 {name=Vin3 value="dc=0 ac=1 sin(0.6, 50m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -30 0 0 {name=l14 lab=GND}
C {devices/lab_pin.sym} 1380 -110 1 0 {name=p15 sig_type=std_logic lab=V_in2}
C {devices/vsource.sym} 1380 -260 0 0 {name=Vin4 value="dc=0 ac=1 sin(0.6, 100m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -210 0 0 {name=l17 lab=GND}
C {devices/lab_pin.sym} 1380 -290 1 0 {name=p18 sig_type=std_logic lab=V_in3}
C {devices/vsource.sym} 1380 -440 0 0 {name=Vin5 value="dc=0 ac=1 sin(0.6, 200m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -390 0 0 {name=l20 lab=GND}
C {devices/lab_pin.sym} 1380 -470 1 0 {name=p21 sig_type=std_logic lab=V_in4}
C {devices/vsource.sym} 1380 -620 0 0 {name=Vin6 value="dc=0 ac=1 sin(0.6, 300m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -570 0 0 {name=l23 lab=GND}
C {devices/lab_pin.sym} 1380 -650 1 0 {name=p24 sig_type=std_logic lab=V_in5}
C {devices/vsource.sym} 1380 -800 0 0 {name=Vin7 value="dc=0 ac=1 sin(0.6, 400m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -750 0 0 {name=l26 lab=GND}
C {devices/lab_pin.sym} 1380 -830 1 0 {name=p27 sig_type=std_logic lab=V_in6}
C {devices/vsource.sym} 1380 -980 0 0 {name=Vin8 value="dc=0 ac=1 sin(0.6, 500m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -930 0 0 {name=l29 lab=GND}
C {devices/lab_pin.sym} 1380 -1010 1 0 {name=p30 sig_type=std_logic lab=V_in7}
C {devices/vsource.sym} 1380 -1150 0 0 {name=Vin1 value="dc=0 ac=1 sin(0.6, 600m, 200k, 0, 0)"}
C {devices/gnd.sym} 1380 -1100 0 0 {name=l9 lab=GND}
C {devices/lab_pin.sym} 1380 -1180 1 0 {name=p10 sig_type=std_logic lab=V_in8}
C {devices/lab_pin.sym} -150 20 0 0 {name=p31 sig_type=std_logic lab=V_in2}
C {devices/lab_pin.sym} -150 60 0 0 {name=p32 sig_type=std_logic lab=en2_p}
C {devices/lab_pin.sym} -150 40 0 0 {name=p33 sig_type=std_logic lab=en2_n}
C {devices/lab_pin.sym} -150 -40 0 0 {name=p34 sig_type=std_logic lab=V_in3}
C {devices/lab_pin.sym} -150 0 0 0 {name=p35 sig_type=std_logic lab=en3_p}
C {devices/lab_pin.sym} -150 -20 0 0 {name=p36 sig_type=std_logic lab=en3_n}
C {devices/lab_pin.sym} -150 -100 0 0 {name=p37 sig_type=std_logic lab=V_in4}
C {devices/lab_pin.sym} -150 -60 0 0 {name=p38 sig_type=std_logic lab=en4_p}
C {devices/lab_pin.sym} -150 -80 0 0 {name=p39 sig_type=std_logic lab=en4_n}
C {devices/lab_pin.sym} -150 -160 0 0 {name=p40 sig_type=std_logic lab=V_in5}
C {devices/lab_pin.sym} -150 -120 0 0 {name=p41 sig_type=std_logic lab=en5_p}
C {devices/lab_pin.sym} -150 -140 0 0 {name=p42 sig_type=std_logic lab=en5_n}
C {devices/lab_pin.sym} -150 -220 0 0 {name=p43 sig_type=std_logic lab=V_in6}
C {devices/lab_pin.sym} -150 -180 0 0 {name=p44 sig_type=std_logic lab=en6_p}
C {devices/lab_pin.sym} -150 -200 0 0 {name=p45 sig_type=std_logic lab=en6_n}
C {devices/lab_pin.sym} -150 -280 0 0 {name=p46 sig_type=std_logic lab=V_in7}
C {devices/lab_pin.sym} -150 -240 0 0 {name=p47 sig_type=std_logic lab=en7_p}
C {devices/lab_pin.sym} -150 -260 0 0 {name=p48 sig_type=std_logic lab=en7_n}
C {devices/lab_pin.sym} -150 -340 0 0 {name=p49 sig_type=std_logic lab=V_in8}
C {devices/lab_pin.sym} -150 -300 0 0 {name=p50 sig_type=std_logic lab=en8_p}
C {devices/lab_pin.sym} -150 -320 0 0 {name=p51 sig_type=std_logic lab=en8_n}
C {devices/lab_pin.sym} -370 -310 2 0 {name=p1 sig_type=std_logic lab=en1_p}
C {devices/lab_pin.sym} -370 -150 2 0 {name=p2 sig_type=std_logic lab=en1_n}
C {devices/lab_pin.sym} -370 -290 2 0 {name=p5 sig_type=std_logic lab=en2_p}
C {devices/lab_pin.sym} -370 -130 2 0 {name=p11 sig_type=std_logic lab=en2_n}
C {devices/lab_pin.sym} -370 -270 2 0 {name=p13 sig_type=std_logic lab=en3_p}
C {devices/lab_pin.sym} -370 -110 2 0 {name=p14 sig_type=std_logic lab=en3_n}
C {devices/lab_pin.sym} -370 -250 2 0 {name=p16 sig_type=std_logic lab=en4_p}
C {devices/lab_pin.sym} -370 -90 2 0 {name=p17 sig_type=std_logic lab=en4_n}
C {devices/lab_pin.sym} -370 -230 2 0 {name=p19 sig_type=std_logic lab=en5_p}
C {devices/lab_pin.sym} -370 -70 2 0 {name=p20 sig_type=std_logic lab=en5_n}
C {devices/lab_pin.sym} -370 -210 2 0 {name=p22 sig_type=std_logic lab=en6_p}
C {devices/lab_pin.sym} -370 -50 2 0 {name=p23 sig_type=std_logic lab=en6_n}
C {devices/lab_pin.sym} -370 -190 2 0 {name=p25 sig_type=std_logic lab=en7_p}
C {devices/lab_pin.sym} -370 -30 2 0 {name=p26 sig_type=std_logic lab=en7_n}
C {devices/lab_pin.sym} -370 -170 2 0 {name=p28 sig_type=std_logic lab=en8_p}
C {devices/lab_pin.sym} -370 -10 2 0 {name=p29 sig_type=std_logic lab=en8_n}
C {adc_bridge1.sym} -590 -200 0 0 {name=A17
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} -590 -180 0 0 {name=A18
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} -590 -160 0 0 {name=A19
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} -590 -140 0 0 {name=A20
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {devices/gnd.sym} -1270 -110 0 0 {name=Vctrl2 lab=GND}
C {devices/lab_pin.sym} -740 -230 1 0 {name=Vctrl3 sig_type=std_logic lab=ctrl_1}
C {devices/gnd.sym} -1050 170 0 0 {name=Vctrl5 lab=GND}
C {devices/lab_pin.sym} -810 -230 1 0 {name=Vctrl6 sig_type=std_logic lab=ctrl_2}
C {devices/gnd.sym} -1120 100 0 0 {name=Vctrl8 lab=GND}
C {devices/lab_pin.sym} -880 -230 1 0 {name=Vctrl9 sig_type=std_logic lab=ctrl_3}
C {devices/gnd.sym} -1200 20 0 0 {name=Vctrl11 lab=GND}
C {devices/lab_pin.sym} -960 -230 1 0 {name=Vctrl12 sig_type=std_logic lab=ctrl_4}
C {devices/gnd.sym} -790 50 0 0 {name=l8 lab=GND
value="dc 0 ac 0 pulse(0 1.2 2u 10n 10n 1u 20u 1)"}
C {decoder.sym} -480 -170 0 0 {name=adut
dut=dut
d_cosim_model=d_cosim
model=./decoder.so
}
C {devices/vsource.sym} -630 110 0 0 {name=Vrst value="dc 0 ac 0 pulse(0 1.2 0 10n 10n 20u 200u 1)"}
C {devices/gnd.sym} -630 140 0 0 {name=l3 lab=GND
value="dc 0 ac 0 pulse(0 1.2 2u 10n 10n 1u 20u 1)"}
C {d_osc.sym} -790 10 0 0 {name=aclock1
clk=clk
d_osc_model=d_osc
freq=200k
}
C {devices/lab_pin.sym} -770 -60 2 0 {name=Vctrl17 sig_type=std_logic lab=clk}
C {devices/lab_pin.sym} -610 -60 2 0 {name=Vctrl18 sig_type=std_logic lab=rst}
C {adc_bridge1.sym} -580 -100 0 0 {name=A21
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} -580 -120 0 0 {name=A22
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {dac_bridge1.sym} -400 -310 0 0 {name=A1
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -290 0 0 {name=A2
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -270 0 0 {name=A3
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -250 0 0 {name=A4
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -230 0 0 {name=A5
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -210 0 0 {name=A6
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -190 0 0 {name=A7
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -170 0 0 {name=A8
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -150 0 0 {name=A9
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -130 0 0 {name=A10
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -110 0 0 {name=A11
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -90 0 0 {name=A12
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -70 0 0 {name=A13
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -50 0 0 {name=A14
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -30 0 0 {name=A15
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} -400 -10 0 0 {name=A16
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {devices/vsource.sym} -1270 -140 0 0 {name=Vrst1 value="dc 0 ac 0 pulse(0 0 40u 10n 10n 150u 200u 1)"}
C {devices/vsource.sym} -1200 -20 0 0 {name=Vrst2 value="dc 0 ac 0 pulse(0 1.2 60u 10n 10n 150u 200u 1)"}
C {devices/vsource.sym} -1120 50 0 0 {name=Vrst3 value="dc 0 ac 0 pulse(0 1.2 80u 10n 10n 150u 200u 1)"}
C {devices/vsource.sym} -1050 120 0 0 {name=Vrst4 value="dc 0 ac 0 pulse(0 1.2 100u 10n 10n 150u 200u 1)"}

488
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/multiplexer_mixed_tb.sch
View File

@ -1,488 +0,0 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
B 2 440 -710 1240 -310 {flags=graph
y2=1.56
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=1.6940659e-21
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0.26
rainbow=0
color="4 5 6 7 8 9 10 12"
node="v_in1
v_in2
v_in3
v_in4
v_in5
v_in6
v_in7
v_in8"}
B 2 440 -1140 1240 -740 {flags=graph
y2=2.86
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=1.6940659e-21
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=1.56
rainbow=0
color="7 12 4 8 4 4 4 9"
node="en1_p
en2_p
en3_p
en4_p
en5_p
en6_p
en7_p
en8_p"
hilight_wave=1}
B 2 440 -290 1240 110 {flags=graph
y2=0.94
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=1.6940659e-21
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0.0004
rainbow=0
color=9
node=v_out}
B 2 440 -1560 1240 -1160 {flags=graph
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=1.6940659e-21
x2=0.00022
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0
rainbow=0
hilight_wave=1
color="4 9"
node="mosi
sck"}
T {
} -210 -250 0 0 0.4 0.4 {}
N 0 -1070 0 -1050 {
lab=GND}
N 370 -710 370 -690 {
lab=V_out}
N 0 -1170 0 -1130 {
lab=Vdd}
N 370 -740 370 -710 {
lab=V_out}
N 120 -980 120 -970 {
lab=#net1}
N 120 -1050 120 -1040 {
lab=Vdd}
N 120 -450 120 -440 {
lab=GND}
N -740 120 -740 140 {
lab=GND}
N -740 50 -740 60 {
lab=V_in1}
N -740 -60 -740 -40 {
lab=GND}
N -740 -240 -740 -220 {
lab=GND}
N -740 -420 -740 -400 {
lab=GND}
N -740 -600 -740 -580 {
lab=GND}
N -740 -780 -740 -760 {
lab=GND}
N -740 -960 -740 -940 {
lab=GND}
N -740 -1130 -740 -1110 {
lab=GND}
N 50 -150 80 -150 {
lab=#net2}
N 50 -170 80 -170 {
lab=#net3}
N 50 -190 80 -190 {
lab=#net4}
N 50 -210 80 -210 {
lab=#net5}
N 50 -230 80 -230 {
lab=#net6}
N 240 -350 340 -350 {
lab=#net7}
N 340 -350 340 -330 {
lab=#net7}
N -490 -230 -490 -210 {
lab=clk}
N -490 -170 -490 -150 {
lab=GND}
N -410 -210 -410 -120 {
lab=rst}
N -280 -230 -10 -230 {
lab=clk}
N -220 -210 -10 -210 {
lab=rst}
N -350 -190 -350 -50 {
lab=sck}
N -290 -170 -290 20 {
lab=mosi}
N -40 -150 -10 -150 {
lab=ss}
N -230 -150 -230 90 {
lab=ss}
N -160 -190 -10 -190 {
lab=sck}
N -100 -170 -10 -170 {
lab=mosi}
N -280 -300 -280 -230 {
lab=clk}
N -490 -230 -280 -230 {
lab=clk}
N -220 -300 -220 -210 {
lab=rst}
N -410 -210 -220 -210 {
lab=rst}
N -160 -300 -160 -190 {
lab=sck}
N -350 -190 -160 -190 {
lab=sck}
N -100 -300 -100 -170 {
lab=mosi}
N -290 -170 -100 -170 {
lab=mosi}
N -40 -300 -40 -150 {
lab=ss}
N -230 -150 -40 -150 {
lab=ss}
N 310 -710 370 -710 {
lab=V_out}
N 310 -710 310 -690 {
lab=V_out}
N 270 -710 310 -710 {
lab=V_out}
C {devices/code_shown.sym} -430 -1220 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt\\
.lib cornerRES.lib res_typ\\
"}
C {devices/code_shown.sym} -440 -1100 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.control
save all
ic V(V_out)=0.6
tran 100n 220u
write tran_res_temp.raw
.endc
"}
C {devices/vsource.sym} 0 -1100 0 0 {name=Vpow value=1.2}
C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
C {devices/launcher.sym} 510 150 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/tran_res_temp.raw tran"
}
C {devices/gnd.sym} 120 -440 0 0 {name=l2 lab=GND}
C {devices/ammeter.sym} 120 -1010 0 0 {name=Vp}
C {devices/gnd.sym} 0 -1050 0 0 {name=l1 lab=GND}
C {devices/lab_pin.sym} 370 -740 1 0 {name=p3 sig_type=std_logic lab=V_out}
C {devices/capa.sym} 370 -660 0 0 {name=C1
m=1
value=100f
footprint=1206
device="ceramic capacitor"}
C {devices/gnd.sym} 370 -630 0 0 {name=l6 lab=GND}
C {devices/lab_pin.sym} 0 -1170 1 0 {name=p4 sig_type=std_logic lab=Vdd}
C {devices/lab_pin.sym} 120 -1050 1 0 {name=p6 sig_type=std_logic lab=Vdd}
C {devices/lab_pin.sym} -30 -520 0 0 {name=p7 sig_type=std_logic lab=V_in1}
C {devices/lab_pin.sym} -30 -480 0 0 {name=p8 sig_type=std_logic lab=en1_p}
C {devices/lab_pin.sym} -30 -500 0 0 {name=p9 sig_type=std_logic lab=en1_n}
C {multiplexer.sym} 120 -710 0 0 {name=x1}
C {devices/vsource.sym} -740 90 0 0 {name=Vin2 value="dc 0 ac 1 sin(0.6, 20m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 140 0 0 {name=l11 lab=GND}
C {devices/lab_pin.sym} -740 50 1 0 {name=p12 sig_type=std_logic lab=V_in1}
C {devices/vsource.sym} -740 -90 0 0 {name=Vin3 value="dc=0 ac=1 sin(0.6, 50m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -40 0 0 {name=l14 lab=GND}
C {devices/lab_pin.sym} -740 -120 1 0 {name=p15 sig_type=std_logic lab=V_in2}
C {devices/vsource.sym} -740 -270 0 0 {name=Vin4 value="dc=0 ac=1 sin(0.6, 100m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -220 0 0 {name=l17 lab=GND}
C {devices/lab_pin.sym} -740 -300 1 0 {name=p18 sig_type=std_logic lab=V_in3}
C {devices/vsource.sym} -740 -450 0 0 {name=Vin5 value="dc=0 ac=1 sin(0.6, 200m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -400 0 0 {name=l20 lab=GND}
C {devices/lab_pin.sym} -740 -480 1 0 {name=p21 sig_type=std_logic lab=V_in4}
C {devices/vsource.sym} -740 -630 0 0 {name=Vin6 value="dc=0 ac=1 sin(0.6, 300m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -580 0 0 {name=l23 lab=GND}
C {devices/lab_pin.sym} -740 -660 1 0 {name=p24 sig_type=std_logic lab=V_in5}
C {devices/vsource.sym} -740 -810 0 0 {name=Vin7 value="dc=0 ac=1 sin(0.6, 400m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -760 0 0 {name=l26 lab=GND}
C {devices/lab_pin.sym} -740 -840 1 0 {name=p27 sig_type=std_logic lab=V_in6}
C {devices/vsource.sym} -740 -990 0 0 {name=Vin8 value="dc=0 ac=1 sin(0.6, 500m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -940 0 0 {name=l29 lab=GND}
C {devices/lab_pin.sym} -740 -1020 1 0 {name=p30 sig_type=std_logic lab=V_in7}
C {devices/vsource.sym} -740 -1160 0 0 {name=Vin1 value="dc=0 ac=1 sin(0.6, 600m, 200k, 0, 0)"}
C {devices/gnd.sym} -740 -1110 0 0 {name=l9 lab=GND}
C {devices/lab_pin.sym} -740 -1190 1 0 {name=p10 sig_type=std_logic lab=V_in8}
C {devices/lab_pin.sym} -30 -580 0 0 {name=p31 sig_type=std_logic lab=V_in2}
C {devices/lab_pin.sym} -30 -540 0 0 {name=p32 sig_type=std_logic lab=en2_p}
C {devices/lab_pin.sym} -30 -560 0 0 {name=p33 sig_type=std_logic lab=en2_n}
C {devices/lab_pin.sym} -30 -640 0 0 {name=p34 sig_type=std_logic lab=V_in3}
C {devices/lab_pin.sym} -30 -600 0 0 {name=p35 sig_type=std_logic lab=en3_p}
C {devices/lab_pin.sym} -30 -620 0 0 {name=p36 sig_type=std_logic lab=en3_n}
C {devices/lab_pin.sym} -30 -700 0 0 {name=p37 sig_type=std_logic lab=V_in4}
C {devices/lab_pin.sym} -30 -660 0 0 {name=p38 sig_type=std_logic lab=en4_p}
C {devices/lab_pin.sym} -30 -680 0 0 {name=p39 sig_type=std_logic lab=en4_n}
C {devices/lab_pin.sym} -30 -760 0 0 {name=p40 sig_type=std_logic lab=V_in5}
C {devices/lab_pin.sym} -30 -720 0 0 {name=p41 sig_type=std_logic lab=en5_p}
C {devices/lab_pin.sym} -30 -740 0 0 {name=p42 sig_type=std_logic lab=en5_n}
C {devices/lab_pin.sym} -30 -820 0 0 {name=p43 sig_type=std_logic lab=V_in6}
C {devices/lab_pin.sym} -30 -780 0 0 {name=p44 sig_type=std_logic lab=en6_p}
C {devices/lab_pin.sym} -30 -800 0 0 {name=p45 sig_type=std_logic lab=en6_n}
C {devices/lab_pin.sym} -30 -880 0 0 {name=p46 sig_type=std_logic lab=V_in7}
C {devices/lab_pin.sym} -30 -840 0 0 {name=p47 sig_type=std_logic lab=en7_p}
C {devices/lab_pin.sym} -30 -860 0 0 {name=p48 sig_type=std_logic lab=en7_n}
C {devices/lab_pin.sym} -30 -940 0 0 {name=p49 sig_type=std_logic lab=V_in8}
C {devices/lab_pin.sym} -30 -900 0 0 {name=p50 sig_type=std_logic lab=en8_p}
C {devices/lab_pin.sym} -30 -920 0 0 {name=p51 sig_type=std_logic lab=en8_n}
C {control.sym} 130 -190 0 0 {name=adut
dut=dut
d_cosim_model= d_cosim
model=./control.so
}
C {devices/lab_pin.sym} 240 -330 2 0 {name=p1 sig_type=std_logic lab=en1_p}
C {devices/lab_pin.sym} 240 -170 2 0 {name=p2 sig_type=std_logic lab=en1_n}
C {devices/lab_pin.sym} 240 -310 2 0 {name=p5 sig_type=std_logic lab=en2_p}
C {devices/lab_pin.sym} 240 -150 2 0 {name=p11 sig_type=std_logic lab=en2_n}
C {devices/lab_pin.sym} 240 -290 2 0 {name=p13 sig_type=std_logic lab=en3_p}
C {devices/lab_pin.sym} 240 -130 2 0 {name=p14 sig_type=std_logic lab=en3_n}
C {devices/lab_pin.sym} 240 -270 2 0 {name=p16 sig_type=std_logic lab=en4_p}
C {devices/lab_pin.sym} 240 -110 2 0 {name=p17 sig_type=std_logic lab=en4_n}
C {devices/lab_pin.sym} 240 -250 2 0 {name=p19 sig_type=std_logic lab=en5_p}
C {devices/lab_pin.sym} 240 -90 2 0 {name=p20 sig_type=std_logic lab=en5_n}
C {devices/lab_pin.sym} 240 -230 2 0 {name=p22 sig_type=std_logic lab=en6_p}
C {devices/lab_pin.sym} 240 -70 2 0 {name=p23 sig_type=std_logic lab=en6_n}
C {devices/lab_pin.sym} 240 -210 2 0 {name=p25 sig_type=std_logic lab=en7_p}
C {devices/lab_pin.sym} 240 -50 2 0 {name=p26 sig_type=std_logic lab=en7_n}
C {devices/lab_pin.sym} 240 -190 2 0 {name=p28 sig_type=std_logic lab=en8_p}
C {devices/lab_pin.sym} 240 -30 2 0 {name=p29 sig_type=std_logic lab=en8_n}
C {adc_bridge1.sym} 20 -230 0 0 {name=A17
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} 20 -210 0 0 {name=A18
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} 20 -190 0 0 {name=A19
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} 20 -170 0 0 {name=A20
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {adc_bridge1.sym} 20 -150 0 0 {name=A21
adc=adc1
adc_bridge_model=adc_bridge
in_low=0.2
in_high=1.0
}
C {devices/capa.sym} 340 -300 0 0 {name=C2
m=1
value=10f
footprint=1206
device="ceramic capacitor"}
C {devices/gnd.sym} 340 -270 0 0 {name=l3 lab=GND}
C {devices/vsource.sym} -410 -90 0 0 {name=Vrst value="dc 0 ac 0 pulse(0 1.2 0 10n 10n 10u 800u)"}
C {d_osc.sym} -490 -190 0 0 {name=aclock1
clk=clk
d_osc_model=d_osc
freq=100k
}
C {devices/vsource.sym} -350 -20 0 0 {name=Vsck value="dc 0 ac 0 pulse(0 1.2 30u 10n 10n 10u 20u 8)"}
C {devices/vsource.sym} -290 50 0 0 {name=Vmosi value="dc 0 ac 0 pulse(0 1.2 62u 10n 10n 20u 80u 1)"}
C {devices/vsource.sym} -230 120 0 0 {name=Vss value="dc 0 ac 0 pulse(1.2 0 20u 10n 10n 170u 200u 1)"}
C {devices/gnd.sym} -490 -150 0 0 {name=l4 lab=GND}
C {devices/gnd.sym} -410 -60 0 0 {name=l7 lab=GND}
C {devices/gnd.sym} -350 10 0 0 {name=l8 lab=GND}
C {devices/gnd.sym} -290 80 0 0 {name=l10 lab=GND}
C {devices/gnd.sym} -230 150 0 0 {name=l12 lab=GND}
C {devices/lab_pin.sym} -280 -300 1 0 {name=p52 sig_type=std_logic lab=clk}
C {devices/lab_pin.sym} -220 -300 1 0 {name=p53 sig_type=std_logic lab=rst}
C {devices/lab_pin.sym} -160 -300 1 0 {name=p54 sig_type=std_logic lab=sck}
C {devices/lab_pin.sym} -100 -300 1 0 {name=p55 sig_type=std_logic lab=mosi}
C {devices/lab_pin.sym} -40 -300 1 0 {name=p56 sig_type=std_logic lab=ss}
C {dac_bridge1.sym} 210 -350 0 0 {name=A1
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -330 0 0 {name=A2
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -310 0 0 {name=A3
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -290 0 0 {name=A4
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -270 0 0 {name=A5
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -250 0 0 {name=A6
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -230 0 0 {name=A7
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -210 0 0 {name=A8
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -190 0 0 {name=A9
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -170 0 0 {name=A10
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -150 0 0 {name=A11
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -130 0 0 {name=A12
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -110 0 0 {name=A13
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -90 0 0 {name=A14
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -70 0 0 {name=A15
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -50 0 0 {name=A16
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {dac_bridge1.sym} 210 -30 0 0 {name=A22
dac=dac1
dac_bridge_model=dac_bridge
out_low=0.0
out_high=1.2
}
C {devices/res.sym} 310 -660 0 0 {name=R1
value=10k
footprint=1206
device=resistor
m=1}
C {devices/gnd.sym} 310 -630 0 0 {name=l13 lab=GND}

289
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/multiplexer_tb.sch
View File

@ -1,289 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
B 2 440 -710 1240 -310 {flags=graph
y2=1.2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1.2e-07
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=3.7e-06
rainbow=0
color="4 4 4 4 4 4 4 4"
node="v_in1
v_in2
v_in3
v_in4
v_in5
v_in6
v_in7
v_in8"}
B 2 440 -1140 1240 -740 {flags=graph
y2=1.3
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1.2e-07
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0
rainbow=0
color="4 7"
node="en1_n
en1_p"}
B 2 440 -290 1240 110 {flags=graph
y2=0.9
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=1.2e-07
divx=5
subdivx=1
dataset=-1
unitx=1
logx=0
logy=0
y1=0.3
rainbow=0
color=9
node=v_out}
N -150 -780 -150 -760 {
lab=GND}
N 250 -110 250 -90 {
lab=V_out}
N -150 -880 -150 -840 {
lab=Vdd}
N 250 -140 250 -110 {
lab=V_out}
N 150 -110 250 -110 {
lab=V_out}
N 0 -380 0 -370 {
lab=#net1}
N 0 -450 0 -440 {
lab=Vdd}
N 0 150 -0 160 {
lab=GND}
N -650 230 -650 250 {
lab=GND}
N -650 160 -650 170 {
lab=en1_p}
N -730 230 -730 250 {
lab=GND}
N -730 160 -730 170 {
lab=en1_n}
N -580 230 -580 250 {
lab=GND}
N -580 160 -580 170 {
lab=V_in1}
N -650 50 -650 70 {
lab=GND}
N -730 50 -730 70 {
lab=GND}
N -580 50 -580 70 {
lab=GND}
N -650 -130 -650 -110 {
lab=GND}
N -730 -130 -730 -110 {
lab=GND}
N -580 -130 -580 -110 {
lab=GND}
N -650 -310 -650 -290 {
lab=GND}
N -730 -310 -730 -290 {
lab=GND}
N -580 -310 -580 -290 {
lab=GND}
N -650 -490 -650 -470 {
lab=GND}
N -730 -490 -730 -470 {
lab=GND}
N -580 -490 -580 -470 {
lab=GND}
N -650 -670 -650 -650 {
lab=GND}
N -730 -670 -730 -650 {
lab=GND}
N -580 -670 -580 -650 {
lab=GND}
N -650 -850 -650 -830 {
lab=GND}
N -730 -850 -730 -830 {
lab=GND}
N -580 -850 -580 -830 {
lab=GND}
N -650 -1020 -650 -1000 {
lab=GND}
N -730 -1020 -730 -1000 {
lab=GND}
N -580 -1020 -580 -1000 {
lab=GND}
C {devices/code_shown.sym} -150 -1100 0 0 {name=MODEL only_toplevel=true
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt\\
.lib cornerRES.lib res_typ\\
"}
C {devices/code_shown.sym} 120 -1100 0 0 {name=NGSPICE only_toplevel=true
value="
.param temp=27
.control
save all
tran 100p 120n
write tran_res_temp.raw
.endc
"}
C {devices/vsource.sym} -150 -810 0 0 {name=Vpow value=1.2}
C {devices/title.sym} -130 260 0 0 {name=l5 author="Copyright 2023 IHP PDK Authors"}
C {devices/launcher.sym} 510 150 0 0 {name=h5
descr="load waves"
tclcommand="xschem raw_read $netlist_dir/tran_res_temp.raw tran"
}
C {devices/gnd.sym} 0 160 0 0 {name=l2 lab=GND}
C {devices/ammeter.sym} 0 -410 0 0 {name=Vp}
C {devices/gnd.sym} -150 -760 0 0 {name=l1 lab=GND}
C {devices/lab_pin.sym} 250 -140 1 0 {name=p3 sig_type=std_logic lab=V_out}
C {devices/capa.sym} 250 -60 0 0 {name=C1
m=1
value=1p
footprint=1206
device="ceramic capacitor"}
C {devices/gnd.sym} 250 -30 0 0 {name=l6 lab=GND}
C {devices/lab_pin.sym} -150 -880 1 0 {name=p4 sig_type=std_logic lab=Vdd}
C {devices/lab_pin.sym} 0 -450 1 0 {name=p6 sig_type=std_logic lab=Vdd}
C {devices/lab_pin.sym} -150 80 0 0 {name=p7 sig_type=std_logic lab=V_in1}
C {devices/lab_pin.sym} -150 120 0 0 {name=p8 sig_type=std_logic lab=en1_p}
C {devices/lab_pin.sym} -150 100 0 0 {name=p9 sig_type=std_logic lab=en1_n}
C {multiplexer.sym} 0 -110 0 0 {name=x1}
C {devices/vsource.sym} -650 200 0 0 {name=Ven2 value=0}
C {devices/gnd.sym} -650 250 0 0 {name=l4 lab=GND}
C {devices/lab_pin.sym} -650 160 1 0 {name=p1 sig_type=std_logic lab=en1_p}
C {devices/vsource.sym} -730 200 0 0 {name=Ven3 value=1.2}
C {devices/gnd.sym} -730 250 0 0 {name=l10 lab=GND}
C {devices/lab_pin.sym} -730 160 1 0 {name=p11 sig_type=std_logic lab=en1_n}
C {devices/vsource.sym} -580 200 0 0 {name=Vin2 value="dc 0 ac 1 sin(0.6, 20m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 250 0 0 {name=l11 lab=GND}
C {devices/lab_pin.sym} -580 160 1 0 {name=p12 sig_type=std_logic lab=V_in1}
C {devices/vsource.sym} -650 20 0 0 {name=Ven4 value=0}
C {devices/gnd.sym} -650 70 0 0 {name=l12 lab=GND}
C {devices/lab_pin.sym} -650 -10 1 0 {name=p13 sig_type=std_logic lab=en2_p}
C {devices/vsource.sym} -730 20 0 0 {name=Ven5 value=1.2}
C {devices/gnd.sym} -730 70 0 0 {name=l13 lab=GND}
C {devices/lab_pin.sym} -730 -10 1 0 {name=p14 sig_type=std_logic lab=en2_n}
C {devices/vsource.sym} -580 20 0 0 {name=Vin3 value="dc=0 ac=1 sin(0.6, 50m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 70 0 0 {name=l14 lab=GND}
C {devices/lab_pin.sym} -580 -10 1 0 {name=p15 sig_type=std_logic lab=V_in2}
C {devices/vsource.sym} -650 -160 0 0 {name=Ven6 value=0}
C {devices/gnd.sym} -650 -110 0 0 {name=l15 lab=GND}
C {devices/lab_pin.sym} -650 -190 1 0 {name=p16 sig_type=std_logic lab=en3_p}
C {devices/vsource.sym} -730 -160 0 0 {name=Ven7 value=1.2}
C {devices/gnd.sym} -730 -110 0 0 {name=l16 lab=GND}
C {devices/lab_pin.sym} -730 -190 1 0 {name=p17 sig_type=std_logic lab=en3_n}
C {devices/vsource.sym} -580 -160 0 0 {name=Vin4 value="dc=0 ac=1 sin(0.6, 100m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 -110 0 0 {name=l17 lab=GND}
C {devices/lab_pin.sym} -580 -190 1 0 {name=p18 sig_type=std_logic lab=V_in3}
C {devices/vsource.sym} -650 -340 0 0 {name=Ven8 value=0}
C {devices/gnd.sym} -650 -290 0 0 {name=l18 lab=GND}
C {devices/lab_pin.sym} -650 -370 1 0 {name=p19 sig_type=std_logic lab=en4_p}
C {devices/vsource.sym} -730 -340 0 0 {name=Ven9 value=1.2}
C {devices/gnd.sym} -730 -290 0 0 {name=l19 lab=GND}
C {devices/lab_pin.sym} -730 -370 1 0 {name=p20 sig_type=std_logic lab=en4_n}
C {devices/vsource.sym} -580 -340 0 0 {name=Vin5 value="dc=0 ac=1 sin(0.6, 200m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 -290 0 0 {name=l20 lab=GND}
C {devices/lab_pin.sym} -580 -370 1 0 {name=p21 sig_type=std_logic lab=V_in4}
C {devices/vsource.sym} -650 -520 0 0 {name=Ven10 value=1.2}
C {devices/gnd.sym} -650 -470 0 0 {name=l21 lab=GND}
C {devices/lab_pin.sym} -650 -550 1 0 {name=p22 sig_type=std_logic lab=en5_p}
C {devices/vsource.sym} -730 -520 0 0 {name=Ven11 value=0}
C {devices/gnd.sym} -730 -470 0 0 {name=l22 lab=GND}
C {devices/lab_pin.sym} -730 -550 1 0 {name=p23 sig_type=std_logic lab=en5_n}
C {devices/vsource.sym} -580 -520 0 0 {name=Vin6 value="dc=0 ac=1 sin(0.6, 300m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 -470 0 0 {name=l23 lab=GND}
C {devices/lab_pin.sym} -580 -550 1 0 {name=p24 sig_type=std_logic lab=V_in5}
C {devices/vsource.sym} -650 -700 0 0 {name=Ven12 value=0}
C {devices/gnd.sym} -650 -650 0 0 {name=l24 lab=GND}
C {devices/lab_pin.sym} -650 -730 1 0 {name=p25 sig_type=std_logic lab=en6_p}
C {devices/vsource.sym} -730 -700 0 0 {name=Ven13 value=1.2}
C {devices/gnd.sym} -730 -650 0 0 {name=l25 lab=GND}
C {devices/lab_pin.sym} -730 -730 1 0 {name=p26 sig_type=std_logic lab=en6_n}
C {devices/vsource.sym} -580 -700 0 0 {name=Vin7 value="dc=0 ac=1 sin(0.6, 400m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 -650 0 0 {name=l26 lab=GND}
C {devices/lab_pin.sym} -580 -730 1 0 {name=p27 sig_type=std_logic lab=V_in6}
C {devices/vsource.sym} -650 -880 0 0 {name=Ven14 value=0}
C {devices/gnd.sym} -650 -830 0 0 {name=l27 lab=GND}
C {devices/lab_pin.sym} -650 -910 1 0 {name=p28 sig_type=std_logic lab=en7_p}
C {devices/vsource.sym} -730 -880 0 0 {name=Ven15 value=1.2}
C {devices/gnd.sym} -730 -830 0 0 {name=l28 lab=GND}
C {devices/lab_pin.sym} -730 -910 1 0 {name=p29 sig_type=std_logic lab=en7_n}
C {devices/vsource.sym} -580 -880 0 0 {name=Vin8 value="dc=0 ac=1 sin(0.6, 500m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 -830 0 0 {name=l29 lab=GND}
C {devices/lab_pin.sym} -580 -910 1 0 {name=p30 sig_type=std_logic lab=V_in7}
C {devices/vsource.sym} -650 -1050 0 0 {name=Ven1 value=0}
C {devices/gnd.sym} -650 -1000 0 0 {name=l3 lab=GND}
C {devices/lab_pin.sym} -650 -1080 1 0 {name=p2 sig_type=std_logic lab=en8_p}
C {devices/vsource.sym} -730 -1050 0 0 {name=Ven16 value=1.2}
C {devices/gnd.sym} -730 -1000 0 0 {name=l7 lab=GND}
C {devices/lab_pin.sym} -730 -1080 1 0 {name=p5 sig_type=std_logic lab=en8_n}
C {devices/vsource.sym} -580 -1050 0 0 {name=Vin1 value="dc=0 ac=1 sin(0.6, 600m, 20meg, 0, 0)"}
C {devices/gnd.sym} -580 -1000 0 0 {name=l9 lab=GND}
C {devices/lab_pin.sym} -580 -1080 1 0 {name=p10 sig_type=std_logic lab=V_in8}
C {devices/lab_pin.sym} -150 20 0 0 {name=p31 sig_type=std_logic lab=V_in2}
C {devices/lab_pin.sym} -150 60 0 0 {name=p32 sig_type=std_logic lab=en2_p}
C {devices/lab_pin.sym} -150 40 0 0 {name=p33 sig_type=std_logic lab=en2_n}
C {devices/lab_pin.sym} -150 -40 0 0 {name=p34 sig_type=std_logic lab=V_in3}
C {devices/lab_pin.sym} -150 0 0 0 {name=p35 sig_type=std_logic lab=en3_p}
C {devices/lab_pin.sym} -150 -20 0 0 {name=p36 sig_type=std_logic lab=en3_n}
C {devices/lab_pin.sym} -150 -100 0 0 {name=p37 sig_type=std_logic lab=V_in4}
C {devices/lab_pin.sym} -150 -60 0 0 {name=p38 sig_type=std_logic lab=en4_p}
C {devices/lab_pin.sym} -150 -80 0 0 {name=p39 sig_type=std_logic lab=en4_n}
C {devices/lab_pin.sym} -150 -160 0 0 {name=p40 sig_type=std_logic lab=V_in5}
C {devices/lab_pin.sym} -150 -120 0 0 {name=p41 sig_type=std_logic lab=en5_p}
C {devices/lab_pin.sym} -150 -140 0 0 {name=p42 sig_type=std_logic lab=en5_n}
C {devices/lab_pin.sym} -150 -220 0 0 {name=p43 sig_type=std_logic lab=V_in6}
C {devices/lab_pin.sym} -150 -180 0 0 {name=p44 sig_type=std_logic lab=en6_p}
C {devices/lab_pin.sym} -150 -200 0 0 {name=p45 sig_type=std_logic lab=en6_n}
C {devices/lab_pin.sym} -150 -280 0 0 {name=p46 sig_type=std_logic lab=V_in7}
C {devices/lab_pin.sym} -150 -240 0 0 {name=p47 sig_type=std_logic lab=en7_p}
C {devices/lab_pin.sym} -150 -260 0 0 {name=p48 sig_type=std_logic lab=en7_n}
C {devices/lab_pin.sym} -150 -340 0 0 {name=p49 sig_type=std_logic lab=V_in8}
C {devices/lab_pin.sym} -150 -300 0 0 {name=p50 sig_type=std_logic lab=en8_p}
C {devices/lab_pin.sym} -150 -320 0 0 {name=p51 sig_type=std_logic lab=en8_n}

BIN
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/simulations/control.so
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Binary file not shown.

90
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/transmission_gate.sch
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@ -1,90 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N 430 -270 540 -270 {
lab=inout_2}
N 430 -420 540 -420 {
lab=inout_2}
N 540 -340 540 -270 {
lab=inout_2}
N 540 -340 580 -340 {
lab=inout_2}
N 540 -420 540 -340 {
lab=inout_2}
N 300 -420 370 -420 {
lab=inout_1}
N 300 -270 370 -270 {
lab=inout_1}
N 300 -340 300 -270 {
lab=inout_1}
N 400 -230 400 -200 {
lab=en_p}
N 400 -490 400 -460 {
lab=en_n}
N 400 -300 400 -270 {
lab=#net1}
N 400 -300 470 -300 {
lab=#net1}
N 400 -390 470 -390 {
lab=#net2}
N 400 -420 400 -390 {
lab=#net2}
N 250 -340 300 -340 {
lab=inout_1}
N 300 -420 300 -340 {
lab=inout_1}
N 250 -490 400 -490 {
lab=en_n}
N 250 -200 400 -200 {
lab=en_p}
N 470 -480 470 -390 {
lab=#net2}
N 470 -640 470 -540 {
lab=vdd}
N 470 -300 470 -210 {
lab=#net1}
N 470 -150 470 -80 {
lab=vss}
C {devices/iopin.sym} 250 -340 2 0 {name=p1 lab=inout_1
}
C {devices/iopin.sym} 580 -340 0 0 {name=p6 lab=inout_2
}
C {devices/ipin.sym} 250 -200 0 0 {name=p2 lab=en_p}
C {devices/iopin.sym} 470 -640 3 0 {name=p3 lab=vdd
}
C {devices/iopin.sym} 470 -80 1 0 {name=p4 lab=vss
}
C {sg13g2_pr/sg13_lv_nmos.sym} 400 -250 3 0 {name=M1
l=0.130u
w=200.0u
ng=20
m=1
model=sg13_lv_nmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 400 -440 1 0 {name=M2
l=0.130u
w=200.0u
ng=20
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {devices/ipin.sym} 250 -490 0 0 {name=p5 lab=en_n}
C {sg13g2_pr/ntap1.sym} 470 -510 0 0 {name=R1
model=ntap1
spiceprefix=X
R=262.847.0
Imax=0.3e-6
}
C {sg13g2_pr/ptap1.sym} 470 -180 2 0 {name=R2
model=ptap1
spiceprefix=X
R=262.847.0
Imax=0.3e-6
}

34
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/transmission_gate.sym
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@ -1,34 +0,0 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -40 130 -40 {}
L 4 -130 40 130 40 {}
L 4 -130 -40 -130 40 {}
L 4 130 -40 130 40 {}
L 4 -150 10 -130 10 {}
L 4 -150 30 -130 30 {}
L 7 0 -60 0 -40 {}
L 7 -150 -20 -130 -20 {}
L 7 130 -20 150 -20 {}
L 7 0 40 0 60 {}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -152.5 7.5 -147.5 12.5 {name=en_n dir=in}
B 5 -152.5 -22.5 -147.5 -17.5 {name=inout_1 dir=inout}
B 5 147.5 -22.5 152.5 -17.5 {name=inout_2 dir=inout}
B 5 -152.5 27.5 -147.5 32.5 {name=en_p dir=in}
B 5 -2.5 57.5 2.5 62.5 {name=vss dir=inout}
T {@symname} -54.5 -6 0 0 0.3 0.3 {}
T {@name} 95 -52 0 0 0.2 0.2 {}
T {vdd} 15 -34 0 1 0.2 0.2 {}
T {en_n} -125 6 0 0 0.2 0.2 {}
T {inout_1} -85 -24 0 1 0.2 0.2 {}
T {inout_2} 125 -24 0 1 0.2 0.2 {}
T {en_p} -125 26 0 0 0.2 0.2 {}
T {vss} 15 26 0 1 0.2 0.2 {}

432
modules/module_3_8_bit_SAR_ADC/test_verilog/multiplexer/xschemrc
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@ -1,432 +0,0 @@
#### xschemrc system configuration file
#### values may be overridden by user's ~/.xschem/xschemrc configuration file
#### or by project-local ./xschemrc
###########################################################################
#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
###########################################################################
#### Normally there is no reason to set this variable if using standard
#### installation. Location of files is set at compile time but may be overridden
#### with following line:
# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
###########################################################################
#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
###########################################################################
#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
# ${HOME}/.xschem/xschem_library
# <install_root>/share/xschem/xschem_library/devices
# <install_root>/share/doc/xschem/examples
# <install_root>/share/doc/xschem/ngspice
# <install_root>/share/doc/xschem/logic
# <install_root>/share/doc/xschem/xschem_simulator
# <install_root>/share/doc/xschem/binto7seg
# <install_root>/share/doc/xschem/pcb
# <install_root>/share/doc/xschem/rom8k
#### Flush any previous definition
set XSCHEM_LIBRARY_PATH {}
#### include devices/*.sym
append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
###########################################################################
#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
###########################################################################
#### each line contains a dircolor(pattern) followed by a color
#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
#### hex code must be enclosed in braces
array unset dircolor
set dircolor(sg13g2_pr$) blue
set dircolor(sg13g2_tests$) blue
set dircolor(xschem_library$) red
set dircolor(devices$) red
###########################################################################
#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
###########################################################################
#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
set netlist_dir $env(PWD)/simulations
#### if this is set to '1' netlists and simulations will go into a simulation/ folder
#### inside the directory containing the top level schematic. Default: not set (0)
# set local_netlist_dir 1
###########################################################################
#### NETLIST AND HIERARCHICAL PRINT EXCLUDE PATTERNS
###########################################################################
#### xschem_libs is a list of patterns of cells to exclude from netlisting.
#### Matching is done as regular expression on full cell path
#### Example:
#### set xschem_libs { {/cmoslib/} {/analoglib/.*pass} buffer }
#### in this case all schematic cells of directory cmoslib and cells containing
#### /analoglib/...pass and buffer will be excluded from netlisting
#### default value: empty
# set xschem_libs {}
#### noprint_libs is a list with same rules as for xschem_libs. This
#### variable controls hierarchical print
#### default value: empty
# set noprint_libs {}
#### nolist_libs is a list with same rules as for xschem_libs. This
#### variable controls cell listing in procedure list_hierarchy.
#### default value: empty
# set nolist_libs {}
###########################################################################
#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
###########################################################################
#### default: empty (use xschem default, [ ])
# set bus_replacement_char {<>}
#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
# set bus_replacement_char {__}
###########################################################################
#### SOME DEFAULT BEHAVIOR
###########################################################################
#### Allowed values: spice, verilog, vhdl, tedax, default: spice
# set netlist_type spice
#### Some netlisting options (these are the defaults)
# set hspice_netlist 1
# set verilog_2001 1
#### to use a fixed line width set change_lw to 0 and set some value to line_width
#### these are the defaults
# set line_width 0
# set change_lw 1
#### allow color postscript and svg exports. Default: 1, enable color
# set color_ps 1
#### set paper size: name, height, width. Sizes in 1/72 of an inch (typographical points)
#### default: {a4 842 595}
# set ps_paper_size {a4 842 595}
# set ps_paper_size {letter 792 612}
#### initial size of xschem window you can specify also position with (wxh+x+y)
#### this is the default:
# set initial_geometry {900x600}
#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
#### allowing to move away by zooming / unzooming with mouse wheel
#### default setting: 0
# set unzoom_nodrift 0
#### if set to 1 full zoom will center the drawing instead of anhoring to lower
#### left corner. Default: 0
set zoom_full_center 1
#### if set to 1 allow to place multiple components with same name.
#### Warning: this is normally not allowed in any simulation netlist.
#### default: 0, do not allow place multiple elements with same name (refdes)
# set disable_unique_names 0
#### if set to 1 continue drawing lines / wires after click
#### default: 0
# set persistent_command 1
#### if set to 1 a wire is inserted when separating components that are
#### connected by pins. Default: not enabled (0)
# set connect_by_kissing 1
#### if set to 1 automatically join/trim wires while editing
#### this may slow down on rally big designs. Can be disabled via menu
#### default: 0
set autotrim_wires 1
#### set widget scaling (mainly for font display), this is useful on 4K displays
#### default: unset (tk uses its default) > 1.0 ==> bigger
# set tk_scaling 1.7
#### use the tclreadline package if available , Default: 1 (enabled).
# set use_tclreadline 1
#### disable some symbol layers. Default: none, all layers are visible.
# set enable_layer(5) 0 ;# example to disable pin red boxes
#### enable to scale grid point size as done with lines at close zoom, default: 0
# set big_grid_points 0
#### enable grouping contiguous bits of bus slices in net->pin instance
#### assignments for verilog netlists. Default: disabled (0)
# set verilog_bitblast 0
#### allow searching the full search path for schematics associated to symbols
#### instead of looking only in symbol directory. Default: disabled (0).
# set search_schematic 0
#### focus the schematic window if mouse goes over it, even if a dialog box
#### is displayed, without needing to click.
#### This allows to move/zoom/pan the schematic while editing attributes.
#### Clicking in the schematic window usually closes the dialog box or starts
#### editing a new component if clicking on a new component.
#### default: enabled (1)
# set autofocus_mainwindow 1
#### set component browser always above drawing canvas.
#### default: enabled (1)
# set component_browser_on_top 0
#### set graph line with multiplier with respect to xschem actual line width
#### default: 2.0
# set graph_linewidth_mult 2.0
###########################################################################
#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
###########################################################################
#### command to translate xpm to png; (assumes command takes source
#### and dest file as arguments, example: gm convert plot.xpm plot.png)
#### default: {gm convert}
#### Windows ghostscript uses gswin64c
# set to_png {gswin64c -sDEVICE=png16m -o}
# set to_png {gm convert}
#### command to translate ps to pdf; (assumes command takes source
#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
#### default: ps2pdf
#### Windows ghostscript uses gswin64c
# set to_pdf {gswin64c -sDEVICE=pdfwrite -o}
# set to_pdf ps2pdf
set to_pdf {ps2pdf -dAutoRotatePages=/None}
###########################################################################
#### UNDO: SAVE ON DISK OR KEEP IN MEMORY
###########################################################################
#### Alloved: 'disk'or 'memory'.
#### Saving undo on disk is safer but slower on extremely big schematics.
#### In most cases you won't notice any delay. Undo on disk allows previous
#### state recovery in case of crashes. In-memory undo is extremely fast
#### but should a crash occur everything is lost.
#### It is highly recommended to keep undo on disk.
#### Default: disk
# set undo_type disk
###########################################################################
#### CUSTOM GRID / SNAP VALUE SETTINGS
###########################################################################
#### Warning: changing these values will likely break compatibility
#### with existing symbol libraries. Defaults: grid 20, snap 10.
# set cadgrid 20
# set cadsnap 10
###########################################################################
#### CUSTOM COLORS MAY BE DEFINED HERE
###########################################################################
# set cadlayers 22
# set light_colors {
# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
# "#ef6158" "#fdb200" }
# set dark_colors {
# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
# "#ef6158" "#fdb200" }
###########################################################################
#### CAIRO STUFF
###########################################################################
#### Scale all fonts by this number
# set cairo_font_scale 1.0
#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
#### match cairo font spacing
# set nocairo_font_xscale 1.0
#### set nocairo_font_yscale 1.0
#### Scale line spacing by this number
# set cairo_font_line_spacing 1.0
#### Specify a font
# set cairo_font_name {Sans-Serif}
# set svg_font_name {Sans-Serif}
#### Lift up text by some zoom-corrected pixels for
#### better compatibility wrt no cairo version.
#### Useful values in the range [-1, 3]
# set cairo_vert_correct 0
# set nocairo_vert_correct 0
###########################################################################
#### KEYBINDINGS
###########################################################################
#### General format for specifying a replacement for a keybind
#### Replace Ctrl-q with Escape (so you wont kill the program)
# set replace_key(Control-q) Escape
#### swap w and W keybinds; Always specify Shift for capital letters
# set replace_key(Shift-W) Key-w
# set replace_key(Key-w) Shift-W
###########################################################################
#### TERMINAL
###########################################################################
#### default for linux: xterm
# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
#### lxterminal is not OK since it will not inherit env vars:
#### In order to reduce memory usage and increase the performance, all instances
#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
###########################################################################
#### EDITOR
###########################################################################
#### editor must not detach from launching shell (-f mandatory for gvim)
#### default for linux: gvim -f
# set editor {gvim -f -geometry 90x28}
# set editor { xterm -geometry 100x40 -e nano }
# set editor { xterm -geometry 100x40 -e pico }
#### For Windows
# set editor {notepad.exe}
###########################################################################
#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
###########################################################################
#### default: 0 (can be enabled by menu)
# set show_infowindow 0
###########################################################################
#### ALWAYS SHOW ERC INFO WINDOW AFTER NETLIST
###########################################################################
#### default: 0
# set show_infowindow_after_netlist 0
###########################################################################
#### TCP CONNECTION WITH GAW
###########################################################################
#### set gaw address for socket connection: {host port}
#### default: set to localhost, port 2020
# set gaw_tcp_address {localhost 2020}
###########################################################################
#### XSCHEM LISTEN TO TCP PORT
###########################################################################
#### set xschem listening port; default: not enabled
# set xschem_listen_port 2021
###########################################################################
#### BESPICE WAVE SOCKET CONNECTION
###########################################################################
#### set bespice wave listening port; default: not enabled
# set bespice_listen_port 2022
###########################################################################
#### TCL FILES TO LOAD AT STARTUP
###########################################################################
#### list of tcl files to preload.
set tcl_files {}
lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
# lappend tcl_files ....
###########################################################################
#### WEB URL DOWNLOAD HELPER APPLICATION
###########################################################################
#### used to download files from web: default: {curl -f -s -O -J}
# set download_url_helper {curl -f -s -O -J}
# set download_url_helper {wget -N --quiet --content-disposition}
###########################################################################
#### XSCHEM TOOLBAR
###########################################################################
#### default: not enabled.
set toolbar_visible 1
# set toolbar_horiz 1
###########################################################################
#### TABBED WINDOWS
###########################################################################
# default: not enabled. Interface can be changed runtime if only one window
# or tab is open.
set tabbed_interface 1
###########################################################################
#### CASE INSENSITIVE SYMBOL LOOKUP
###########################################################################
## this option might be useful on filesystems that are case insensitive and
## on designs ported from windows where case of file names does not matter.
## if this option is set symbol lookup will be case insensitive,
## so a symbol reference 'AMPLI.SYM' will match with 'ampli.sym' or
## Amply.sym on disk. File system must be case insensitive for this to work,
## like FAT32 or NTFS.
## Do not set this option if you don't know what you are doing.
## Default: not enabled (0)
# set case_insensitive 1
###########################################################################
#### HIDE GRAPHS IF NO SPICE DATA LOADED
###########################################################################
## if enabled graphs will be hidden if no data is loaded.
## default: not enabled (0)
# set hide_empty_graphs 0
###########################################################################
#### SHOW HIDDEN TEXTS
###########################################################################
## This option shows text objects even if they have attribute 'hide=true' set
## default: 0 (not set)
# set show_hidden_texts 1
###########################################################################
#### LIVE BACKANNOTATION OF DATA AT CURSOR 2 (B) POSITION
###########################################################################
## if enabled will backannotate values in schematic at cursor 'b' position
## in graph. Default: not enabled (0)
set live_cursor2_backannotate 1
###########################################################################
#### IHP PDK SPECIFIC VARIABLES
###########################################################################
## check if env var PDK_ROOT exists, and use it for building open_pdks paths
if { [info exists env(PDK_ROOT)] && $env(PDK_ROOT) ne {} } {
## found variable, set tcl PDK_ROOT var
if {![file isdir $env(PDK_ROOT)]} {
puts stderr "Warning: PDK_ROOT environment variable is set but path not found on the system."
}
set PDK_ROOT $env(PDK_ROOT)
} else {
## not existing or empty.
puts stderr "Warning: PDK_ROOT env. var. not found or empty, trying to find an open_pdks install"
if {[file isdir /usr/share/pdk]} {set PDK_ROOT /usr/share/pdk
} elseif {[file isdir /usr/local/share/pdk]} {set PDK_ROOT /usr/local/share/pdk
} elseif {[file isdir $env(HOME)/share/pdk]} {set PDK_ROOT $env(HOME)/share/pdk
} else {
puts stderr {No open_pdks installation found, set PDK_ROOT env. var. and restart xschem}
}
}
if {[info exists PDK_ROOT]} {
## get process variant
if {[info exists env(PDK)]} {
set PDK $env(PDK)
} else {
set PDK ihp-sg13g2
}
set SG13G2_MODELS ${PDK_ROOT}/${PDK}/libs.tech/ngspice/models
set SG13G2_MODELS_XYCE ${PDK_ROOT}/${PDK}/libs.tech/xyce/models
puts stderr "SG13G2_MODELS: $SG13G2_MODELS"
puts stderr "SG13G2_MODELS_XYCE: $SG13G2_MODELS_XYCE"
#puts stderr "SKYWATER_STDCELLS: $SG13G2_STDCELLS"
}
# open_pdks specific:
# Set variables after ${PDK_ROOT} is known
# This overrides some of the variables set above.
set XSCHEM_START_WINDOW ${PDK_ROOT}/${PDK}/libs.tech/xschem/sg13g2_tests/IHP_testcases.sch
append XSCHEM_LIBRARY_PATH :${PDK_ROOT}/${PDK}/libs.tech/xschem
# allow a user-specific path add-on (https://github.com/iic-jku/iic-osic-tools/issues/7)
if { [info exists ::env(XSCHEM_USER_LIBRARY_PATH) ] } {
append XSCHEM_LIBRARY_PATH :$env(XSCHEM_USER_LIBRARY_PATH)
}

45
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/Makefile
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@ -1,45 +0,0 @@
# Define variables
IVERILOG = iverilog
VVP = vvp
GTKWAVE = gtkwave
NGSPICE = ngspice
OUTPUT = ctrl.out
MIXED = control.so
MIXED_OBJ = control_obj_dir
VCD_FILE = control_tb.vcd
SRC_FILES = control.v spi.v control_tb.v
NGSPICE_FILE = control.v
DEST_DIR = ../../xschem/multiplexer/simulations
# Default target
all: run_wave
# Compile using iverilog
$(OUTPUT): $(SRC_FILES)
$(IVERILOG) -o $(OUTPUT) $(SRC_FILES)
# Run the simulation with vvp
run: $(OUTPUT)
$(VVP) $(OUTPUT)
copy:
cp $(MIXED) $(DEST_DIR)
# Open the wave file in GTKWave
wave: $(VCD_FILE)
$(GTKWAVE) $(VCD_FILE) conf.gtkw
# Run ngspice vlnggen command
ngspice:
$(NGSPICE) vlnggen $(NGSPICE_FILE)
# Execute both the simulation and wave viewer
run_wave: run wave
# Run ngspice and then the rest of the steps
full: ngspice run_wave copy
# Clean up generated files
clean:
rm -f $(OUTPUT) $(VCD_FILE) $(MIXED)
rm -rf $(MIXED_OBJ)

30
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/conf.gtkw
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@ -1,30 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
[*] Fri Sep 27 14:29:16 2024
[*]
[dumpfile] "/home/herman/tmp/AnalogMux-Workshop/design_data/verilog/spi/control_tb.vcd"
[dumpfile_mtime] "Fri Sep 27 14:28:09 2024"
[dumpfile_size] 3045
[savefile] "/home/herman/tmp/AnalogMux-Workshop/design_data/verilog/spi/conf.gtkw"
[timestart] 0
[size] 1906 985
[pos] -1 -1
*-15.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] control_tb.
[sst_width] 269
[signals_width] 118
[sst_expanded] 1
[sst_vpaned_height] 291
@28
control_tb.clk
control_tb.rst
@29
control_tb.ss
@28
control_tb.sck
control_tb.mosi
@22
control_tb.dout_p[7:0]
control_tb.dout_n[7:0]
[pattern_trace] 1
[pattern_trace] 0

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modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control.v
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@ -1,35 +0,0 @@
module control(
input clk,
input rst,
input sck,
input mosi,
input ss,
output miso,
output [7:0] dout_p,
output [7:0] dout_n
);
reg [7:0] in_reg;
wire [7:0] dout;
wire done;
assign dout_p = dout;
assign dout_n = ~dout;
// Instantiate the SPI slave module
spi uut (
.clk(clk),
.rst(rst),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sck(sck),
.done(done),
.din(in_reg),
.dout(dout)
);
endmodule

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103
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng.cpp
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@ -1,103 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts)
#include "Vlng__pch.h"
//============================================================
// Constructors
Vlng::Vlng(VerilatedContext* _vcontextp__, const char* _vcname__)
: VerilatedModel{*_vcontextp__}
, vlSymsp{new Vlng__Syms(contextp(), _vcname__, this)}
, clk{vlSymsp->TOP.clk}
, rst{vlSymsp->TOP.rst}
, sck{vlSymsp->TOP.sck}
, mosi{vlSymsp->TOP.mosi}
, ss{vlSymsp->TOP.ss}
, miso{vlSymsp->TOP.miso}
, dout_p{vlSymsp->TOP.dout_p}
, dout_n{vlSymsp->TOP.dout_n}
, rootp{&(vlSymsp->TOP)}
{
// Register model with the context
contextp()->addModel(this);
}
Vlng::Vlng(const char* _vcname__)
: Vlng(Verilated::threadContextp(), _vcname__)
{
}
//============================================================
// Destructor
Vlng::~Vlng() {
delete vlSymsp;
}
//============================================================
// Evaluation function
#ifdef VL_DEBUG
void Vlng___024root___eval_debug_assertions(Vlng___024root* vlSelf);
#endif // VL_DEBUG
void Vlng___024root___eval_static(Vlng___024root* vlSelf);
void Vlng___024root___eval_initial(Vlng___024root* vlSelf);
void Vlng___024root___eval_settle(Vlng___024root* vlSelf);
void Vlng___024root___eval(Vlng___024root* vlSelf);
void Vlng::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vlng::eval_step\n"); );
#ifdef VL_DEBUG
// Debug assertions
Vlng___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif // VL_DEBUG
vlSymsp->__Vm_deleter.deleteAll();
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
vlSymsp->__Vm_didInit = true;
VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
Vlng___024root___eval_static(&(vlSymsp->TOP));
Vlng___024root___eval_initial(&(vlSymsp->TOP));
Vlng___024root___eval_settle(&(vlSymsp->TOP));
}
VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
Vlng___024root___eval(&(vlSymsp->TOP));
// Evaluate cleanup
Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
}
//============================================================
// Events and timing
bool Vlng::eventsPending() { return false; }
uint64_t Vlng::nextTimeSlot() {
VL_FATAL_MT(__FILE__, __LINE__, "", "No delays in the design");
return 0;
}
//============================================================
// Utilities
const char* Vlng::name() const {
return vlSymsp->name();
}
//============================================================
// Invoke final blocks
void Vlng___024root___eval_final(Vlng___024root* vlSelf);
VL_ATTR_COLD void Vlng::final() {
Vlng___024root___eval_final(&(vlSymsp->TOP));
}
//============================================================
// Implementations of abstract methods from VerilatedModel
const char* Vlng::hierName() const { return vlSymsp->name(); }
const char* Vlng::modelName() const { return "Vlng"; }
unsigned Vlng::threads() const { return 1; }
void Vlng::prepareClone() const { contextp()->prepareClone(); }
void Vlng::atClone() const {
contextp()->threadPoolpOnClone();
}

95
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng.h
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary model header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef VERILATED_VLNG_H_
#define VERILATED_VLNG_H_ // guard
#include "verilated.h"
class Vlng__Syms;
class Vlng___024root;
// This class is the main interface to the Verilated model
class alignas(VL_CACHE_LINE_BYTES) Vlng VL_NOT_FINAL : public VerilatedModel {
private:
// Symbol table holding complete model state (owned by this class)
Vlng__Syms* const vlSymsp;
public:
// CONSTEXPR CAPABILITIES
// Verilated with --trace?
static constexpr bool traceCapable = false;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(&clk,0,0);
VL_IN8(&rst,0,0);
VL_IN8(&sck,0,0);
VL_IN8(&mosi,0,0);
VL_IN8(&ss,0,0);
VL_OUT8(&miso,0,0);
VL_OUT8(&dout_p,7,0);
VL_OUT8(&dout_n,7,0);
// CELLS
// Public to allow access to /* verilator public */ items.
// Otherwise the application code can consider these internals.
// Root instance pointer to allow access to model internals,
// including inlined /* verilator public_flat_* */ items.
Vlng___024root* const rootp;
// CONSTRUCTORS
/// Construct the model; called by application code
/// If contextp is null, then the model will use the default global context
/// If name is "", then makes a wrapper with a
/// single model invisible with respect to DPI scope names.
explicit Vlng(VerilatedContext* contextp, const char* name = "TOP");
explicit Vlng(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
virtual ~Vlng();
private:
VL_UNCOPYABLE(Vlng); ///< Copying not allowed
public:
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step.
void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes.
void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion.
void final();
/// Are there scheduled events to handle?
bool eventsPending();
/// Returns time at next time slot. Aborts if !eventsPending()
uint64_t nextTimeSlot();
/// Trace signals in the model; called by application code
void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) { contextp()->trace(tfp, levels, options); }
/// Retrieve name of this model instance (as passed to constructor).
const char* name() const;
// Abstract methods from VerilatedModel
const char* hierName() const override final;
const char* modelName() const override final;
unsigned threads() const override final;
/// Prepare for cloning the model at the process level (e.g. fork in Linux)
/// Release necessary resources. Called before cloning.
void prepareClone() const;
/// Re-init after cloning the model at the process level (e.g. fork in Linux)
/// Re-allocate necessary resources. Called after cloning.
void atClone() const;
private:
// Internal functions - trace registration
void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);
};
#endif // guard

76
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng.mk
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@ -1,76 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vlng.mk
default: Vlng
### Constants...
# Perl executable (from $PERL, defaults to 'perl' if not set)
PERL = perl
# Python3 executable (from $PYTHON3, defaults to 'python3' if not set)
PYTHON3 = python3
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# C++ code coverage 0/1 (from --prof-c)
VM_PROFC = 0
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vlng
# Module prefix (from --prefix)
VM_MODPREFIX = Vlng
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-I/usr/local/share/ngspice/scripts/src \
-fpic \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
verilator_main \
verilator_shim \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
.. \
../../../../../../../../../usr/local/share/ngspice/scripts/src \
### Default rules...
# Include list of all generated classes
include Vlng_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
verilator_main.o: /usr/local/share/ngspice/scripts/src/verilator_main.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
verilator_shim.o: /usr/local/share/ngspice/scripts/src/verilator_shim.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vlng: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
# Verilated -*- Makefile -*-

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modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng__ALL.cpp
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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vlng.cpp"
#include "Vlng___024root__DepSet_h9def6047__0.cpp"
#include "Vlng___024root__DepSet_h26a4896e__0.cpp"
#include "Vlng___024root__Slow.cpp"
#include "Vlng___024root__DepSet_h9def6047__0__Slow.cpp"
#include "Vlng___024root__DepSet_h26a4896e__0__Slow.cpp"
#include "Vlng__Syms.cpp"

10
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng__ALL.d
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@ -1,10 +0,0 @@
Vlng__ALL.o: Vlng__ALL.cpp Vlng.cpp Vlng__pch.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_config.h \
/usr/local/share/verilator/include/verilated_types.h \
/usr/local/share/verilator/include/verilated_funcs.h Vlng__Syms.h Vlng.h \
Vlng___024root.h Vlng___024root__DepSet_h9def6047__0.cpp \
Vlng___024root__DepSet_h26a4896e__0.cpp Vlng___024root__Slow.cpp \
Vlng___024root__DepSet_h9def6047__0__Slow.cpp \
Vlng___024root__DepSet_h26a4896e__0__Slow.cpp Vlng__Syms.cpp

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modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng__Syms.cpp
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vlng__pch.h"
#include "Vlng.h"
#include "Vlng___024root.h"
// FUNCTIONS
Vlng__Syms::~Vlng__Syms()
{
}
Vlng__Syms::Vlng__Syms(VerilatedContext* contextp, const char* namep, Vlng* modelp)
: VerilatedSyms{contextp}
// Setup internal state of the Syms class
, __Vm_modelp{modelp}
// Setup module instances
, TOP{this, namep}
{
// Check resources
Verilated::stackCheck(18);
// Configure time unit / time precision
_vm_contextp__->timeunit(-12);
_vm_contextp__->timeprecision(-12);
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOP.__Vconfigure(true);
}

38
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng__Syms.h
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef VERILATED_VLNG__SYMS_H_
#define VERILATED_VLNG__SYMS_H_ // guard
#include "verilated.h"
// INCLUDE MODEL CLASS
#include "Vlng.h"
// INCLUDE MODULE CLASSES
#include "Vlng___024root.h"
// SYMS CLASS (contains all model state)
class alignas(VL_CACHE_LINE_BYTES)Vlng__Syms final : public VerilatedSyms {
public:
// INTERNAL STATE
Vlng* const __Vm_modelp;
VlDeleter __Vm_deleter;
bool __Vm_didInit = false;
// MODULE INSTANCE STATE
Vlng___024root TOP;
// CONSTRUCTORS
Vlng__Syms(VerilatedContext* contextp, const char* namep, Vlng* modelp);
~Vlng__Syms();
// METHODS
const char* name() { return TOP.name(); }
};
#endif // guard

59
modules/module_3_8_bit_SAR_ADC/test_verilog/spi/control_obj_dir/Vlng___024root.h
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vlng.h for the primary calling header
#ifndef VERILATED_VLNG___024ROOT_H_
#define VERILATED_VLNG___024ROOT_H_ // guard
#include "verilated.h"
class Vlng__Syms;
class alignas(VL_CACHE_LINE_BYTES) Vlng___024root final : public VerilatedModule {
public:
// DESIGN SPECIFIC STATE
VL_IN8(clk,0,0);
VL_IN8(rst,0,0);
VL_IN8(sck,0,0);
VL_IN8(mosi,0,0);
VL_IN8(ss,0,0);
VL_OUT8(miso,0,0);
VL_OUT8(dout_p,7,0);
VL_OUT8(dout_n,7,0);
CData/*7:0*/ control__DOT__in_reg;
CData/*0:0*/ control__DOT__uut__DOT__mosi_q;
CData/*0:0*/ control__DOT__uut__DOT__ss_q;
CData/*0:0*/ control__DOT__uut__DOT__sck_q;
CData/*0:0*/ control__DOT__uut__DOT__sck_old_q;
CData/*7:0*/ control__DOT__uut__DOT__data_d;
CData/*7:0*/ control__DOT__uut__DOT__data_q;
CData/*2:0*/ control__DOT__uut__DOT__bit_ct_d;
CData/*2:0*/ control__DOT__uut__DOT__bit_ct_q;
CData/*7:0*/ control__DOT__uut__DOT__dout_d;
CData/*7:0*/ control__DOT__uut__DOT__dout_q;
CData/*0:0*/ control__DOT__uut__DOT__miso_d;
CData/*0:0*/ control__DOT__uut__DOT__miso_q;
CData/*0:0*/ __VstlFirstIteration;
CData/*0:0*/ __Vtrigprevexpr___TOP__clk__0;
CData/*0:0*/ __VactContinue;
IData/*31:0*/ __VactIterCount;
VlTriggerVec<1> __VstlTriggered;
VlTriggerVec<1> __VactTriggered;
VlTriggerVec<1> __VnbaTriggered;
// INTERNAL VARIABLES
Vlng__Syms* const vlSymsp;
// CONSTRUCTORS
Vlng___024root(Vlng__Syms* symsp, const char* v__name);
~Vlng___024root();
VL_UNCOPYABLE(Vlng___024root);
// INTERNAL METHODS
void __Vconfigure(bool first);
};
#endif // guard

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