create content

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_ref.sch

@@ -1,153 +0,0 @@
-v {xschem version=3.4.5 file_version=1.2
-}
-G {}
-K {}
-V {}
-S {}
-E {}
-N 270 -480 500 -480 {
-lab=#net1}
-N 540 -480 550 -480 {
-lab=vdd}
-N 550 -510 550 -480 {
-lab=vdd}
-N 540 -510 550 -510 {
-lab=vdd}
-N 500 -480 500 -470 {
-lab=#net1}
-N 500 -470 740 -470 {
-lab=#net1}
-N 740 -480 740 -470 {
-lab=#net1}
-N 230 -530 230 -480 {
-lab=vdd}
-N 540 -530 780 -530 {
-lab=vdd}
-N 780 -530 780 -480 {
-lab=vdd}
-N 540 -530 540 -510 {
-lab=vdd}
-N 230 -530 540 -530 {
-lab=vdd}
-N 780 -450 780 -410 {
-lab=VBG}
-N 780 -410 870 -410 {
-lab=VBG}
-N 780 -410 780 -380 {
-lab=VBG}
-N 780 -530 870 -530 {
-lab=vdd}
-N 540 -450 540 -280 {
-lab=#net2}
-N 430 -280 540 -280 {
-lab=#net2}
-N 230 -280 350 -280 {
-lab=#net3}
-N 230 -450 230 -280 {
-lab=#net3}
-N 230 -280 230 -160 {
-lab=#net3}
-N 140 -280 230 -280 {
-lab=#net3}
-N 140 -220 140 -200 {
-lab=GND}
-N 780 -320 780 -300 {
-lab=GND}
-N 540 -280 640 -280 {
-lab=#net2}
-N 640 -220 640 -200 {
-lab=GND}
-N 540 -220 540 -160 {
-lab=#net4}
-N 230 -100 230 -70 {
-lab=GND}
-N 190 -130 190 -70 {
-lab=GND}
-N 500 -130 500 -70 {
-lab=GND}
-N 540 -100 540 -70 {
-lab=GND}
-C {sg13g2_pr/sg13_lv_pmos.sym} 250 -480 0 1 {name=M3
-l=0.6u
-w=65u
-ng=8
-m=1
-model=sg13_lv_pmos
-spiceprefix=X
-}
-C {sg13g2_pr/sg13_lv_pmos.sym} 520 -480 0 0 {name=M4
-l=0.6u
-w=65u
-ng=8
-m=1
-model=sg13_lv_pmos
-spiceprefix=X
-}
-C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym} 390 -380 1 1 {name=U1 model=diff_amp_cell spiceprefix=X}
-C {sg13g2_pr/sg13_lv_pmos.sym} 760 -480 0 0 {name=M5
-l=0.6u
-w=65u
-ng=8
-m=1
-model=sg13_lv_pmos
-spiceprefix=X
-}
-C {opin.sym} 870 -410 0 0 {name=p1 lab=VBG}
-C {res.sym} 780 -350 0 0 {name=R4
-value=16k
-footprint=1206
-device=resistor
-m=1}
-C {lab_pin.sym} 870 -530 0 1 {name=p2 sig_type=std_logic lab=vdd}
-C {res.sym} 140 -250 0 0 {name=R3
-value=45k
-footprint=1206
-device=resistor
-m=1}
-C {gnd.sym} 140 -200 0 0 {name=l1 lab=GND}
-C {gnd.sym} 780 -300 0 0 {name=l2 lab=GND}
-C {res.sym} 540 -250 0 0 {name=R1
-value=2.145k
-footprint=1206
-device=resistor
-m=1}
-C {res.sym} 640 -250 0 0 {name=R2
-value=45k
-footprint=1206
-device=resistor
-m=1}
-C {gnd.sym} 640 -200 0 0 {name=l3 lab=GND}
-C {sg13g2_pr/pnpMPA.sym} 210 -130 0 0 {name=Q1
-model=pnpMPA
-spiceprefix=X
-w=5.0u
-l=5.0u
-}
-C {sg13g2_pr/pnpMPA.sym} 520 -130 0 0 {name=Q2
-model=pnpMPA
-spiceprefix=X
-w=40.0u
-l=5.0u
-}
-C {gnd.sym} 540 -70 0 0 {name=l4 lab=GND}
-C {gnd.sym} 500 -70 0 0 {name=l5 lab=GND}
-C {gnd.sym} 230 -70 0 0 {name=l6 lab=GND}
-C {gnd.sym} 190 -70 0 0 {name=l7 lab=GND}
-C {devices/code_shown.sym} -430 -260 0 0 {name=MODEL only_toplevel=true
-format="tcleval( @value )"
-value="
-.lib $::SG13G2_MODELS/cornerHBT.lib hbt_typ
-.lib cornerMOSlv.lib mos_tt
-"}
-C {devices/code_shown.sym} -450 -520 0 0 {name=NGSPICE1 DC Vbe Sim only_toplevel=true 
-value="
-.control
-.save all
-op
-dc TEMP -50 100 5
-set wr_singlescale
-set wr_vecnames
-wrdata vbe_tempvar.txt VBG
-.endc
-
-"}

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch

@@ -0,0 +1,319 @@
+v {xschem version=3.4.5 file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N -720 -850 -720 -795 {
+lab=#net1}
+N -575 -980 -485 -980 {
+lab=vdd}
+N -645 -930 -615 -930 {
+lab=#net1}
+N -720 -850 -645 -850 {
+lab=#net1}
+N -720 -900 -720 -850 {
+lab=#net1}
+N -645 -930 -645 -850 {
+lab=#net1}
+N -680 -930 -645 -930 {
+lab=#net1}
+N -720 -765 -720 -710 {
+lab=GND}
+N -575 -850 -575 -795 {
+lab=#net2}
+N -720 -710 -575 -710 {
+lab=GND}
+N -575 -735 -575 -710 {
+lab=GND}
+N -680 -765 -485 -765 {
+lab=v-}
+N -485 -980 -485 -850 {
+lab=vdd}
+N -575 -850 -525 -850 {
+lab=#net2}
+N -575 -900 -575 -850 {
+lab=#net2}
+N -485 -765 -485 -650 {
+lab=v-}
+N -485 -820 -485 -765 {
+lab=v-}
+N -110 -695 -80 -695 {
+lab=Vo1}
+N -275 -795 -275 -760 {
+lab=vdd}
+N -350 -610 -350 -595 {
+lab=#net3}
+N -350 -535 -275 -535 {
+lab=GND}
+N -275 -535 -275 -520 {
+lab=GND}
+N -275 -630 -275 -535 {
+lab=GND}
+N -435 -735 -410 -735 {
+lab=v+}
+N -485 -650 -410 -650 {
+lab=v-}
+N -780 -930 -720 -930 {
+lab=vdd}
+N -575 -930 -530 -930 {
+lab=vdd}
+N -575 -980 -575 -960 {
+lab=vdd}
+N -720 -980 -575 -980 {
+lab=vdd}
+N -720 -980 -720 -960 {
+lab=vdd}
+N 1085 -665 1085 -620 {
+lab=vdd}
+N 1085 -560 1085 -530 {
+lab=GND}
+N 370 -560 390 -560 {
+lab=#net4}
+N 370 -620 370 -560 {
+lab=#net4}
+N 370 -620 430 -620 {
+lab=#net4}
+N 130 -560 130 -460 {
+lab=GND}
+N 280 -460 430 -460 {
+lab=GND}
+N 130 -740 230 -740 {
+lab=v-}
+N 280 -965 280 -940 {
+lab=vdd}
+N 130 -940 280 -940 {
+lab=vdd}
+N 130 -840 130 -740 {
+lab=v-}
+N 430 -750 430 -740 {
+lab=v+}
+N 430 -740 430 -710 {
+lab=v+}
+N 430 -560 430 -460 {
+lab=GND}
+N 430 -620 430 -590 {
+lab=#net4}
+N 430 -650 430 -620 {
+lab=#net4}
+N 280 -460 280 -430 {
+lab=GND}
+N 130 -460 280 -460 {
+lab=GND}
+N 170 -870 390 -870 {
+lab=Vo1}
+N 595 -900 595 -870 {
+lab=Vo1}
+N 430 -750 595 -750 {
+lab=v+}
+N 980 -770 1030 -770 {
+lab=VBG}
+N 635 -840 635 -770 {
+lab=VBG}
+N 315 -740 430 -740 {
+lab=v+}
+N 430 -840 430 -750 {
+lab=v+}
+N 595 -750 595 -710 {
+lab=v+}
+N 430 -460 595 -460 {
+lab=GND}
+N 595 -650 595 -460 {
+lab=GND}
+N 430 -940 635 -940 {
+lab=vdd}
+N 980 -655 980 -460 {
+lab=GND}
+N 800 -460 980 -460 {
+lab=GND}
+N 980 -770 980 -715 {
+lab=VBG}
+N 800 -770 980 -770 {
+lab=VBG}
+N 635 -940 635 -900 {
+lab=vdd}
+N 635 -870 725 -870 {
+lab=vdd}
+N 430 -940 430 -900 {
+lab=vdd}
+N 280 -940 430 -940 {
+lab=vdd}
+N 430 -870 495 -870 {
+lab=vdd}
+N 130 -940 130 -900 {
+lab=vdd}
+N 70 -870 130 -870 {
+lab=vdd}
+N 130 -740 130 -590 {
+lab=v-}
+N 170 -560 315 -560 {
+lab=v+}
+N 315 -740 315 -560 {
+lab=v+}
+N 800 -770 800 -715 {
+lab=VBG}
+N 635 -770 800 -770 {
+lab=VBG}
+N 800 -655 800 -460 {
+lab=GND}
+N 595 -460 800 -460 {
+lab=GND}
+N 1200 -540 1250 -540 {
+lab=sub!}
+N 1200 -480 1200 -465 {
+lab=GND}
+C {devices/code_shown.sym} -415 -305 0 0 {name=COMMANDS2 only_toplevel=true value="
+.control
+.save all
+op
+dc TEMP -50 100 5
+.endc
+"
+}
+C {devices/code_shown.sym} -420 -455 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
+.lib $::SG13G2_MODELS/cornerRES.lib res_typ
+.lib cornerMOSlv.lib mos_tt
+"}
+C {sg13g2_pr/sg13_lv_nmos.sym} -700 -765 2 0 {name=M6
+l=10u
+w=150n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} -700 -930 0 1 {name=M7
+l=1u
+w=1u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} -595 -930 0 0 {name=M8
+l=1u
+w=1u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {gnd.sym} -720 -710 0 0 {name=l1 lab=GND}
+C {capa.sym} -575 -765 0 0 {name=C2
+m=1
+value=500e-15
+footprint=1206
+device="ceramic capacitor"}
+C {sg13g2_pr/sg13_lv_pmos.sym} -505 -850 0 0 {name=M9
+l=4u
+w=200n
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} -485 -980 0 1 {name=p5 sig_type=std_logic lab=vdd}
+C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} -260 -695 0 0 {name=x2}
+C {lab_pin.sym} -275 -795 0 1 {name=p1 sig_type=std_logic lab=vdd}
+C {gnd.sym} -275 -520 0 1 {name=l4 lab=GND}
+C {isource.sym} -350 -565 0 1 {name=I1 value=80u}
+C {iopin.sym} -435 -735 0 1 {name=p16 lab=v+}
+C {iopin.sym} -435 -650 3 1 {name=p7 lab=v-}
+C {iopin.sym} -80 -695 0 0 {name=p10 lab=Vo1}
+C {lab_pin.sym} -530 -930 0 1 {name=p4 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -780 -930 0 0 {name=p17 sig_type=std_logic lab=vdd}
+C {vsource.sym} 1085 -590 0 0 {name=V1 value=1.2 savecurrent=false}
+C {lab_pin.sym} 1085 -665 0 1 {name=p6 sig_type=std_logic lab=vdd}
+C {gnd.sym} 1085 -530 0 0 {name=l18 lab=GND}
+C {sg13g2_pr/sg13_lv_nmos.sym} 150 -560 2 0 {name=M2
+l=5u
+w=7.14u
+ng=4
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_nmos.sym} 410 -560 2 1 {name=M3
+l=5u
+w=21u
+ng=8
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {gnd.sym} 280 -430 0 0 {name=l3 lab=GND}
+C {sg13g2_pr/sg13_lv_pmos.sym} 150 -870 0 1 {name=M5
+l=5u
+w=15u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 410 -870 0 0 {name=M1
+l=5u
+w=15u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 280 -965 0 1 {name=p2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 230 -740 3 0 {name=p3 sig_type=std_logic lab=v-}
+C {lab_pin.sym} 315 -740 0 0 {name=p8 sig_type=std_logic lab=v+}
+C {lab_pin.sym} 285 -870 1 1 {name=p9 sig_type=std_logic lab=Vo1}
+C {sg13g2_pr/sg13_lv_pmos.sym} 615 -870 0 0 {name=M4
+l=5u
+w=16u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {opin.sym} 1030 -770 0 0 {name=p11 lab=VBG}
+C {lab_pin.sym} 595 -900 2 1 {name=p12 sig_type=std_logic lab=Vo1}
+C {lab_pin.sym} 70 -870 0 0 {name=p13 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 495 -870 0 1 {name=p14 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 725 -870 0 1 {name=p15 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/cap_cmim.sym} 980 -685 0 0 {name=C3
+model=cap_cmim
+w=25.8e-6
+l=25.8e-6
+m=1
+spiceprefix=X}
+C {sg13g2_pr/rppd.sym} 430 -680 0 0 {name=R3
+w=0.5e-6
+l=194.345e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1
+}
+C {sg13g2_pr/rppd.sym} 595 -680 0 0 {name=R1
+w=0.5e-6
+l=194.345e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1.2
+}
+C {sg13g2_pr/rppd.sym} 800 -685 0 0 {name=R2
+w=0.5e-6
+l=192.395e-6
+model=rppd
+spiceprefix=X
+b=0
+m=1
+}
+C {sg13g2_pr/ptap1.sym} 1200 -510 2 0 {name=R4
+model=ptap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {lab_pin.sym} 1250 -540 2 0 {name=p18 sig_type=std_logic lab=sub!}
+C {gnd.sym} 1200 -465 0 0 {name=l2 lab=GND}

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/simulations/vgs_delta_tempvar.txt

@@ -0,0 +1,32 @@
+ temp-sweep      vgs            
+-5.00000000e+01  3.47898007e-01 
+-4.50000000e+01  3.46241573e-01 
+-4.00000000e+01  3.44576875e-01 
+-3.50000000e+01  3.42903290e-01 
+-3.00000000e+01  3.41220282e-01 
+-2.50000000e+01  3.39527318e-01 
+-2.00000000e+01  3.37823875e-01 
+-1.50000000e+01  3.36109440e-01 
+-1.00000000e+01  3.34383506e-01 
+-5.00000000e+00  3.32645580e-01 
+ 0.00000000e+00  3.30895179e-01 
+ 5.00000000e+00  3.29131833e-01 
+ 1.00000000e+01  3.27355082e-01 
+ 1.50000000e+01  3.25564484e-01 
+ 2.00000000e+01  3.23759608e-01 
+ 2.50000000e+01  3.21940038e-01 
+ 3.00000000e+01  3.20105373e-01 
+ 3.50000000e+01  3.18255227e-01 
+ 4.00000000e+01  3.16389230e-01 
+ 4.50000000e+01  3.14507025e-01 
+ 5.00000000e+01  3.12608275e-01 
+ 5.50000000e+01  3.10692654e-01 
+ 6.00000000e+01  3.08759856e-01 
+ 6.50000000e+01  3.06809589e-01 
+ 7.00000000e+01  3.04841578e-01 
+ 7.50000000e+01  3.02855566e-01 
+ 8.00000000e+01  3.00851313e-01 
+ 8.50000000e+01  2.98828600e-01 
+ 9.00000000e+01  2.96787225e-01 
+ 9.50000000e+01  2.94727011e-01 
+ 1.00000000e+02  2.92647805e-01 

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/vbesim.sch

@@ -1,66 +0,0 @@
-v {xschem version=3.4.5 file_version=1.2
-}
-G {}
-K {}
-V {}
-S {}
-E {}
-N 180 -100 180 -80 {
-lab=GND}
-N 180 -240 180 -200 {
-lab=Vbe}
-N 180 -240 360 -240 {
-lab=Vbe}
-N 360 -150 360 -140 {
-lab=#net1}
-N 360 -80 360 -70 {
-lab=GND}
-N 360 -240 360 -210 {
-lab=Vbe}
-N 140 -170 140 -100 {
-lab=GND}
-N 140 -100 180 -100 {
-lab=GND}
-N 180 -140 180 -100 {
-lab=GND}
-N 80 -240 180 -240 {
-lab=Vbe}
-N 80 -180 80 -160 {
-lab=GND}
-N 360 -240 410 -240 {
-lab=Vbe}
-C {devices/gnd.sym} 180 -80 0 0 {name=l1 lab=GND}
-C {devices/gnd.sym} 80 -160 0 0 {name=l2 lab=GND}
-C {devices/gnd.sym} 360 -70 0 0 {name=l3 lab=GND}
-C {devices/code_shown.sym} -370 -420 0 0 {name=NGSPICE DC Vbe Sim only_toplevel=true 
-value="
-.control
-.save #net1
-.save #net2
-op
-dc TEMP -50 100 5
-set wr_singlescale
-set wr_vecnames
-wrdata vbe_tempvar.txt Vbe
-.endc
-
-"}
-C {res.sym} 80 -210 0 0 {name=R1
-value=45k
-footprint=1206
-device=resistor
-m=1}
-C {isource.sym} 360 -180 2 0 {name=I0 value=25e-6}
-C {sg13g2_pr/pnpMPA.sym} 160 -170 0 0 {name=Q2
-model=pnpMPA
-spiceprefix=X
-w=5.0u
-l=5.0u
-}
-C {vsource.sym} 360 -110 0 0 {name=V1 value=1.2 savecurrent=false}
-C {devices/code_shown.sym} -460 -90 0 0 {name=MODEL only_toplevel=true
-format="tcleval( @value )"
-value="
-.lib $::SG13G2_MODELS/cornerHBT.lib hbt_typ
-"}
-C {lab_pin.sym} 410 -240 0 1 {name=p1 sig_type=std_logic lab=Vbe}

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.va

@@ -8,7 +8,7 @@ output electrical out;
 
 input electrical IN1, IN2;
 
-parameter real gain = 10; // setting gain to 10 of the differential amplifier
+parameter real gain = 10000; // setting gain to 10 of the differential amplifier
 
 analog begin
 

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.va

@@ -0,0 +1,21 @@
+// importing libs
+
+`include "discipline.h"
+
+module diff_amp (out, IN1, IN2);
+
+output electrical out; 
+
+input electrical IN1, IN2;
+
+parameter real gain = 10000; // setting gain to 10 of the differential amplifier
+
+analog begin
+
+    V(out) <+ gain * (V(IN1) - V(IN2));
+
+end
+
+endmodule
+
+

modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym

@@ -1,9 +1,7 @@
-v {xschem version=3.4.6RC file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 
 }
-
 G {}
-
 K {type=opamp_va
 
 format="@spiceprefix@name @@OUT @@IN1 @@IN2 @model"
@@ -32,44 +30,28 @@ N1 out in1 in2 diff_amp_model
 
 * following line specifies the location for the .osdi file so ngspice can use it.
 
-pre_osdi /home/pedersen/chipdesign/cmos_analog/opensource_analog_course/bgr_bjt/verilog/diff_amp.osdi
+pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.osdi
 
 .endc
 
 )"
 
 }
-
 V {}
-
 S {}
-
 E {}
-
 L 4 -100 -40 -80 -40 {}
-
 L 4 80 0 100 0 {}
-
 L 4 -100 40 -80 40 {}
-
 B 5 97.5 -2.5 102.5 2.5 {name=OUT dir=out}
-
 B 5 -102.5 -42.5 -97.5 -37.5 {name=IN1 dir=in}
-
 B 5 -102.5 37.5 -97.5 42.5 {name=IN2 dir=in}
-
 P 4 4 -80 80 -80 -80 80 -0 -80 80 {}
-
 T {@symname} -64 -6 0 0 0.3 0.3 {}
-
 T {@name} 85 -22 0 0 0.2 0.2 {}
-
 T {IN1} -75 -44 0 0 0.2 0.2 {}
-
 T {OUT} 65 -4 0 1 0.2 0.2 {}
-
 T {IN2} -75 36 0 0 0.2 0.2 {}
-
 T {Ensure port order matches the
 
 order in the verilog-A file.} -30 -70 0 0 0.1 0.1 {hide=instance}