luke
/
IHP-AnalogAcademy
mirror of https://github.com/IHP-GmbH/IHP-AnalogAcademy.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

remove verilogA amp

This commit is contained in:
PhillipRambo 2025-05-06 09:29:47 +02:00
parent 0e0fc01c3e
commit 87b3e3b029
1 changed files with 0 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
modules/module_1_bandgap_reference/part_1_OTA/testbenches/ota_testbench.sch
View File

@ -200,22 +200,6 @@ N 95 200 200 200 {
lab=#net4}
N 95 260 95 280 {
lab=GND}
N 1300 330 1570 330 {
lab=vout3}
N 1180 330 1245 330 {
lab=#net5}
N 1180 390 1180 400 {
lab=GND}
N 1410 120 1570 120 {
lab=vout3}
N 1570 120 1570 330 {
lab=vout3}
N 1180 160 1210 160 {
lab=#net5}
N 1180 160 1180 330 {
lab=#net5}
N 1110 80 1210 80 {
lab=vp}
C {vsource.sym} 775 -205 0 0 {name=V1 value="DC 0.6 AC 1 0"
}
C {vsource.sym} 1010 -205 0 0 {name=VDD value="DC 1.2"}
@ -310,20 +294,6 @@ C {lab_pin.sym} 335 65 0 0 {name=p8 sig_type=std_logic lab=VDDac}
C {vsource.sym} 95 230 0 0 {name=V4 value="DC 0.6"
}
C {gnd.sym} 95 280 0 0 {name=l12 lab=GND}
C {ind.sym} 1275 330 1 0 {name=L16
m=1
value=4G
footprint=1206
device=inductor}
C {capa.sym} 1180 360 0 0 {name=C3
m=1
value=4G
footprint=1206
device="ceramic capacitor"}
C {gnd.sym} 1180 400 0 0 {name=l17 lab=GND}
C {iopin.sym} 1570 120 0 0 {name=p9 lab=vout3}
C {lab_pin.sym} 1110 80 0 0 {name=p14 sig_type=std_logic lab=vp}
C {two_stage_OTA.sym} 360 -410 0 0 {name=x1}
C {two_stage_OTA.sym} 350 240 0 0 {name=x2}
C {two_stage_OTA.sym} 1305 -255 0 0 {name=x3}
C {diff_amp.sym} 1310 120 0 0 {name=U1 model=diff_amp_cell spiceprefix=X}