upload gds files

modules/module_0_foundations/inverter/inverter.sch

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+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 410 -190 410 -130 {lab=Gnd}
+N 410 -340 410 -280 {lab=Vdd}
+N 330 -280 370 -280 {lab=Vin}
+N 330 -280 330 -190 {lab=Vin}
+N 330 -190 370 -190 {lab=Vin}
+N 410 -230 490 -230 {lab=Vout}
+N 410 -230 410 -220 {lab=Vout}
+N 410 -250 410 -230 {lab=Vout}
+C {sg13g2_pr/sg13_lv_nmos.sym} 390 -190 2 1 {name=M1
+l=0.45u
+w=1.0u
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 390 -280 0 0 {name=M2
+l=0.45u
+w=2.0u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {iopin.sym} 490 -230 2 1 {name=p2 lab=Vout}
+C {iopin.sym} 410 -340 2 0 {name=p5 lab=Vdd}
+C {iopin.sym} 330 -240 2 0 {name=p6 lab=Vin}
+C {iopin.sym} 410 -130 2 1 {name=p1 lab=Gnd}

modules/module_0_foundations/inverter/inverter.sym

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+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 7 -70 -80 -70 -60 {}
+L 7 -150 0 -130 0 {}
+L 7 110 0 130 0 {}
+L 7 -70 70 -70 90 {}
+B 5 -72.5 -82.5 -67.5 -77.5 {name=Vdd dir=inout}
+B 5 -152.5 -2.5 -147.5 2.5 {name=Vin dir=inout}
+B 5 127.5 -2.5 132.5 2.5 {name=Vout dir=inout}
+B 5 -72.5 87.5 -67.5 92.5 {name=Gnd dir=inout}
+A 4 105 0 7.071067811865476 135 360 {}
+P 4 5 100 0 -130 -80 -130 90 100 0 100 0 {}
+T {@symname} -84 -6 0 0 0.3 0.3 {}
+T {@name} -45 -32 0 0 0.2 0.2 {}
+T {Vdd} -74 -55 3 1 0.2 0.2 {}
+T {Vin} -125 -4 0 0 0.2 0.2 {}
+T {Vout} 80 -9 0 1 0.2 0.2 {}
+T {Gnd} -66 65 1 1 0.2 0.2 {}

modules/module_0_foundations/inverter/inverter_tb.sch

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+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 710 -550 1510 -150 {flags=graph
+y1=-0.0023
+y2=1.3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=2e-06
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=vout
+color=4
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+N 150 -170 150 -140 {lab=Vin}
+N 70 -170 70 -140 {lab=Vdd}
+N 70 -80 70 -60 {lab=GND}
+N 110 -60 150 -60 {lab=GND}
+N 150 -80 150 -60 {lab=GND}
+N 110 -60 110 -50 {lab=GND}
+N 70 -60 110 -60 {lab=GND}
+N 320 -410 320 -380 {lab=Vdd}
+N 320 -210 320 -190 {lab=GND}
+N 220 -300 240 -300 {lab=Vin}
+N 520 -300 540 -300 {lab=Vout}
+C {vsource.sym} 150 -110 0 0 {name=V1 value="PULSE(0 1.2 0.5u 10n 10n 1u 2u 1)" savecurrent=false}
+C {vsource.sym} 70 -110 0 0 {name=V2 value=1.2 savecurrent=false}
+C {gnd.sym} 110 -50 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 150 -170 0 0 {name=p1 sig_type=std_logic lab=Vin}
+C {lab_pin.sym} 70 -170 0 0 {name=p3 sig_type=std_logic lab=Vdd}
+C {code_shown.sym} 40 -540 0 0 {name=NGSPICE
+only_toplevel=true
+value="
+.control
+save all
+tran 50n 2u 
+write test_inverter.raw
+.endc
+" }
+C {devices/code_shown.sym} 280 -540 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib cornerMOSlv.lib mos_tt
+"}
+C {launcher.sym} 770 -120 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_inverter.raw tran"
+}
+C {inverter.sym} 390 -300 0 0 {name=x1}
+C {lab_pin.sym} 220 -300 0 0 {name=p2 sig_type=std_logic lab=Vin}
+C {gnd.sym} 320 -190 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 320 -410 0 0 {name=p4 sig_type=std_logic lab=Vdd}
+C {lab_pin.sym} 540 -300 0 1 {name=p5 sig_type=std_logic lab=Vout}
+C {lab_pin.sym} -210 -140 0 0 {name=p6 sig_type=std_logic lab=Vin}

modules/module_0_foundations/xschem/simulations/nmos_gmid.spice

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-** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/xschem/nmos_gmid.sch
-**.subckt nmos_gmid
-XM3 net1 net2 GND GND sg13_lv_nmos w=3.33u l=3.25u ng=1 m=1
-Vdd1 net1 GND 0.6
-Vdd2 net2 GND 0.27
-**** begin user architecture code
-
-.lib cornerMOSlv.lib mos_tt
-
-
-
-.control
-op
-write output_file.raw
-.endc
-
-
-**** end user architecture code
-**.ends
-.GLOBAL GND
-.end

modules/module_0_foundations/xschem/simulations/nmos_intrin.spice

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-** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_0_foundations/xschem/nmos_intrin.sch
-**.subckt nmos_intrin
-XM2 Vout net2 GND GND sg13_lv_nmos w=46.54 l=3.25u ng=1 m=5
-I1 Vdd net1 13.96e-6
-XM5 net1 net1 GND GND sg13_lv_nmos w=46.54 l=3.25u ng=1 m=5
-Vdd Vdd GND 1.2
-C1 Vout GND 1p m=1
-Vin net1 net2 AC
-**** begin user architecture code
-
-.lib cornerMOSlv.lib mos_tt
-
-
-
-.control
-op
-ac dec 20 1 1e9
-save all
-let Av = db(v(vout))
-write output_file.raw
-.endc
-
-
-**** end user architecture code
-**.ends
-.GLOBAL GND
-.end

utils/gds_files/README.md

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+Open Run GDS Files - Tapeout November 2024
+
+This directory contains layout files for the Open Run in the IHP TO_Nov2024 project.
+
+Overview
+
+These files represent designs submitted for the November 2024 tapeout at IHP. They include layouts for various chips and circuit designs developed by contributors in the open-source community.
+
+Acknowledgments
+
+A huge thanks to everyone who contributed to this project—your effort and dedication made this possible!
+
+📁 Directory Contents:
+
+GDSII layout files (.gds, .gds.gz, etc.)
+
+Chip designs prepared for fabrication
+
+For more details, visit the GitHub repository.