Rearrange the EM section along with documentation

modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/Tcon_post_sim.dat.xyce

@@ -0,0 +1,969 @@
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+</dep>
+<dep V(VCC) FREQ>
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+</dep>
+<dep V(VIN) FREQ>
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+</dep>
+<dep V(VOUT) FREQ>
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+</dep>

modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/Tcon_post_sim.net

@@ -0,0 +1,402 @@
+
+.SUBCKT IHP_PDK_nonlinear_components_npn13G2  gnd c b e bn Nx=1  
+X1 c b e bn npn13G2 Nx={Nx} 
+.ENDS
+  
+
+* EQUIVALENT CIRCUIT FOR VECTOR FITTED S-MATRIX
+* Created using scikit-rf vectorFitting.py
+*
+.SUBCKT s_equivalent_1 p1 p2 p3
+*
+* Port network for port 1
+V1 p1 s1 0
+R1 s1 0 50.0
+Gd1_1 0 s1 p1 0 1.252159491849092e-06
+Fd1_1 0 s1 V1 6.260797459245461e-05
+Gr1_re_1_1 0 s1 x1_re_a1 0 992321637841.9834
+Gr1_im_1_1 0 s1 x1_im_a1 0 2081723191810.322
+Gr2_1_1 0 s1 x2_a1 0 31931065058.0284
+Gr3_1_1 0 s1 x3_a1 0 26696149.77524791
+Gr4_1_1 0 s1 x4_a1 0 -4424836184.122385
+Gd1_2 0 s1 p2 0 -6.245592515696785e-07
+Fd1_2 0 s1 V2 -3.1227962578483925e-05
+Gr1_re_1_2 0 s1 x1_re_a2 0 -132118566386.80286
+Gr1_im_1_2 0 s1 x1_im_a2 0 -1407465757793.0315
+Gr2_1_2 0 s1 x2_a2 0 65790489213.10337
+Gr3_1_2 0 s1 x3_a2 0 -11103650.452407794
+Gr4_1_2 0 s1 x4_a2 0 2336915043.823303
+Gd1_3 0 s1 p3 0 -8.287572210408101e-07
+Fd1_3 0 s1 V3 -4.143786105204051e-05
+Gr1_re_1_3 0 s1 x1_re_a3 0 91061486096.70384
+Gr1_im_1_3 0 s1 x1_im_a3 0 -1366526533444.829
+Gr2_1_3 0 s1 x2_a3 0 -97199529707.57573
+Gr3_1_3 0 s1 x3_a3 0 -41828064.97162587
+Gr4_1_3 0 s1 x4_a3 0 2498264859.301965
+*
+* State networks driven by port 1
+Cx1_re_a1 x1_re_a1 0 1.0
+Gx1_re_a1 0 x1_re_a1 p1 0 0.1414213562373095
+Fx1_re_a1 0 x1_re_a1 V1 7.0710678118654755
+Rp1_re_re_a1 0 x1_re_a1 1.472812708330351e-13
+Gp1_re_im_a1 0 x1_re_a1 x1_im_a1 0 4842390011821.618
+Cx1_im_a1 x1_im_a1 0 1.0
+Gp1_im_re_a1 0 x1_im_a1 x1_re_a1 0 -4842390011821.618
+Rp1_im_im_a1 0 x1_im_a1 1.472812708330351e-13
+Cx2_a1 x2_a1 0 1.0
+Gx2_a1 0 x2_a1 p1 0 0.07071067811865475
+Fx2_a1 0 x2_a1 V1 3.5355339059327378
+Rp2_a1 0 x2_a1 2.3132900074484617e-13
+Cx3_a1 x3_a1 0 1.0
+Gx3_a1 0 x3_a1 p1 0 0.07071067811865475
+Fx3_a1 0 x3_a1 V1 3.5355339059327378
+Rp3_a1 0 x3_a1 5.7343873896109026e-12
+Cx4_a1 x4_a1 0 1.0
+Gx4_a1 0 x4_a1 p1 0 0.07071067811865475
+Fx4_a1 0 x4_a1 V1 3.5355339059327378
+Rp4_a1 0 x4_a1 1.1050289223907674e-12
+*
+* Port network for port 2
+V2 p2 s2 0
+R2 s2 0 50.0
+Gd2_1 0 s2 p1 0 -6.227985429374527e-07
+Fd2_1 0 s2 V1 -3.113992714687264e-05
+Gr1_re_2_1 0 s2 x1_re_a1 0 -132215340952.91939
+Gr1_im_2_1 0 s2 x1_im_a1 0 -1408980246075.243
+Gr2_2_1 0 s2 x2_a1 0 64949356275.529495
+Gr3_2_1 0 s2 x3_a1 0 -11221014.506834837
+Gr4_2_1 0 s2 x4_a1 0 2339786554.526249
+Gd2_2 0 s2 p2 0 1.254032247867132e-06
+Fd2_2 0 s2 V2 6.27016123933566e-05
+Gr1_re_2_2 0 s2 x1_re_a2 0 993468976807.2136
+Gr1_im_2_2 0 s2 x1_im_a2 0 2082275021781.5044
+Gr2_2_2 0 s2 x2_a2 0 31295864080.54669
+Gr3_2_2 0 s2 x3_a2 0 26922295.703447904
+Gr4_2_2 0 s2 x4_a2 0 -4425523979.209311
+Gd2_3 0 s2 p3 0 -8.26934398006074e-07
+Fd2_3 0 s2 V3 -4.13467199003037e-05
+Gr1_re_2_3 0 s2 x1_re_a3 0 90612204239.09584
+Gr1_im_2_3 0 s2 x1_im_a3 0 -1367270919142.5
+Gr2_2_3 0 s2 x2_a3 0 -97270630350.73973
+Gr3_2_3 0 s2 x3_a3 0 -41819532.06381788
+Gr4_2_3 0 s2 x4_a3 0 2499020365.3723636
+*
+* State networks driven by port 2
+Cx1_re_a2 x1_re_a2 0 1.0
+Gx1_re_a2 0 x1_re_a2 p2 0 0.1414213562373095
+Fx1_re_a2 0 x1_re_a2 V2 7.0710678118654755
+Rp1_re_re_a2 0 x1_re_a2 1.472812708330351e-13
+Gp1_re_im_a2 0 x1_re_a2 x1_im_a2 0 4842390011821.618
+Cx1_im_a2 x1_im_a2 0 1.0
+Gp1_im_re_a2 0 x1_im_a2 x1_re_a2 0 -4842390011821.618
+Rp1_im_im_a2 0 x1_im_a2 1.472812708330351e-13
+Cx2_a2 x2_a2 0 1.0
+Gx2_a2 0 x2_a2 p2 0 0.07071067811865475
+Fx2_a2 0 x2_a2 V2 3.5355339059327378
+Rp2_a2 0 x2_a2 2.3132900074484617e-13
+Cx3_a2 x3_a2 0 1.0
+Gx3_a2 0 x3_a2 p2 0 0.07071067811865475
+Fx3_a2 0 x3_a2 V2 3.5355339059327378
+Rp3_a2 0 x3_a2 5.7343873896109026e-12
+Cx4_a2 x4_a2 0 1.0
+Gx4_a2 0 x4_a2 p2 0 0.07071067811865475
+Fx4_a2 0 x4_a2 V2 3.5355339059327378
+Rp4_a2 0 x4_a2 1.1050289223907674e-12
+*
+* Port network for port 3
+V3 p3 s3 0
+R3 s3 0 50.0
+Gd3_1 0 s3 p1 0 -5.850489639125378e-07
+Fd3_1 0 s3 V1 -2.925244819562689e-05
+Gr1_re_3_1 0 s3 x1_re_a1 0 92536926822.98253
+Gr1_im_3_1 0 s3 x1_im_a1 0 -1359678417204.1968
+Gr2_3_1 0 s3 x2_a1 0 -94375091593.95485
+Gr3_3_1 0 s3 x3_a1 0 -42702727.10445669
+Gr4_3_1 0 s3 x4_a1 0 2512831531.3397083
+Gd3_2 0 s3 p2 0 -5.827058523744099e-07
+Fd3_2 0 s3 V2 -2.91352926187205e-05
+Gr1_re_3_2 0 s3 x1_re_a2 0 91994687321.63583
+Gr1_im_3_2 0 s3 x1_im_a2 0 -1359271117954.837
+Gr2_3_2 0 s3 x2_a2 0 -93661293675.16116
+Gr3_3_2 0 s3 x3_a2 0 -42551693.91981165
+Gr4_3_2 0 s3 x4_a2 0 2510163084.773589
+Gd3_3 0 s3 p3 0 1.7454513280235063e-06
+Fd3_3 0 s3 V3 8.727256640117532e-05
+Gr1_re_3_3 0 s3 x1_re_a3 0 769960443999.756
+Gr1_im_3_3 0 s3 x1_im_a3 0 2060751911128.5803
+Gr2_3_3 0 s3 x2_a3 0 206561443521.5676
+Gr3_3_3 0 s3 x3_a3 0 60645607.64178932
+Gr4_3_3 0 s3 x4_a3 0 -4673003947.699802
+*
+* State networks driven by port 3
+Cx1_re_a3 x1_re_a3 0 1.0
+Gx1_re_a3 0 x1_re_a3 p3 0 0.1414213562373095
+Fx1_re_a3 0 x1_re_a3 V3 7.0710678118654755
+Rp1_re_re_a3 0 x1_re_a3 1.472812708330351e-13
+Gp1_re_im_a3 0 x1_re_a3 x1_im_a3 0 4842390011821.618
+Cx1_im_a3 x1_im_a3 0 1.0
+Gp1_im_re_a3 0 x1_im_a3 x1_re_a3 0 -4842390011821.618
+Rp1_im_im_a3 0 x1_im_a3 1.472812708330351e-13
+Cx2_a3 x2_a3 0 1.0
+Gx2_a3 0 x2_a3 p3 0 0.07071067811865475
+Fx2_a3 0 x2_a3 V3 3.5355339059327378
+Rp2_a3 0 x2_a3 2.3132900074484617e-13
+Cx3_a3 x3_a3 0 1.0
+Gx3_a3 0 x3_a3 p3 0 0.07071067811865475
+Fx3_a3 0 x3_a3 V3 3.5355339059327378
+Rp3_a3 0 x3_a3 5.7343873896109026e-12
+Cx4_a3 x4_a3 0 1.0
+Gx4_a3 0 x4_a3 p3 0 0.07071067811865475
+Fx4_a3 0 x4_a3 V3 3.5355339059327378
+Rp4_a3 0 x4_a3 1.1050289223907674e-12
+.ENDS s_equivalent_1
+
+.SUBCKT T_connection _net0 _net2 _net1 
+XT_connection _net0 _net2 _net1 s_equivalent_1 
+.ENDS
+
+* EQUIVALENT CIRCUIT FOR VECTOR FITTED S-MATRIX
+* Created using scikit-rf vectorFitting.py
+*
+.SUBCKT s_equivalent_0 p1 p2 p3 p4
+*
+* Port network for port 1
+V1 p1 s1 0
+R1 s1 0 50.0
+Gd1_1 0 s1 p1 0 2.893139271665703e-06
+Fd1_1 0 s1 V1 0.00014465696358328516
+Gr1_1_1 0 s1 x1_a1 0 4912147948453.049
+Gr2_re_1_1 0 s1 x2_re_a1 0 -1319268556079.9465
+Gr2_im_1_1 0 s1 x2_im_a1 0 1735174622789.5796
+Gr3_1_1 0 s1 x3_a1 0 -80979426.93577664
+Gr4_1_1 0 s1 x4_a1 0 -3817759930.7041607
+Gd1_2 0 s1 p2 0 -8.407909559144355e-07
+Fd1_2 0 s1 V2 -4.2039547795721777e-05
+Gr1_1_2 0 s1 x1_a2 0 -1207829434525.9895
+Gr2_re_1_2 0 s1 x2_re_a2 0 382577355417.01276
+Gr2_im_1_2 0 s1 x2_im_a2 0 -388533785357.56036
+Gr3_1_2 0 s1 x3_a2 0 104571502.07414089
+Gr4_1_2 0 s1 x4_a2 0 -3867803750.0574265
+Gd1_3 0 s1 p3 0 -1.665917931625849e-06
+Fd1_3 0 s1 V3 -8.329589658129245e-05
+Gr1_1_3 0 s1 x1_a3 0 1436697289427.5513
+Gr2_re_1_3 0 s1 x2_re_a3 0 -1051013779449.3003
+Gr2_im_1_3 0 s1 x2_im_a3 0 -1420073398137.625
+Gr3_1_3 0 s1 x3_a3 0 147369695.643702
+Gr4_1_3 0 s1 x4_a3 0 2337796707.3133445
+Gd1_4 0 s1 p4 0 3.818220753214489e-06
+Fd1_4 0 s1 V4 0.0001909110376607245
+Gr1_1_4 0 s1 x1_a4 0 -597334113507.8119
+Gr2_re_1_4 0 s1 x2_re_a4 0 216495732485.25082
+Gr2_im_1_4 0 s1 x2_im_a4 0 -143460916711.4927
+Gr3_1_4 0 s1 x3_a4 0 -58188130.45721889
+Gr4_1_4 0 s1 x4_a4 0 2798174572.1720953
+*
+* State networks driven by port 1
+Cx1_a1 x1_a1 0 1.0
+Gx1_a1 0 x1_a1 p1 0 0.07071067811865475
+Fx1_a1 0 x1_a1 V1 3.5355339059327378
+Rp1_a1 0 x1_a1 1.4249470243021733e-13
+Cx2_re_a1 x2_re_a1 0 1.0
+Gx2_re_a1 0 x2_re_a1 p1 0 0.1414213562373095
+Fx2_re_a1 0 x2_re_a1 V1 7.0710678118654755
+Rp2_re_re_a1 0 x2_re_a1 2.2370881216791236e-13
+Gp2_re_im_a1 0 x2_re_a1 x2_im_a1 0 4303319264264.5474
+Cx2_im_a1 x2_im_a1 0 1.0
+Gp2_im_re_a1 0 x2_im_a1 x2_re_a1 0 -4303319264264.5474
+Rp2_im_im_a1 0 x2_im_a1 2.2370881216791236e-13
+Cx3_a1 x3_a1 0 1.0
+Gx3_a1 0 x3_a1 p1 0 0.07071067811865475
+Fx3_a1 0 x3_a1 V1 3.5355339059327378
+Rp3_a1 0 x3_a1 5.911834241884773e-12
+Cx4_a1 x4_a1 0 1.0
+Gx4_a1 0 x4_a1 p1 0 0.07071067811865475
+Fx4_a1 0 x4_a1 V1 3.5355339059327378
+Rp4_a1 0 x4_a1 1.036388375239062e-12
+*
+* Port network for port 2
+V2 p2 s2 0
+R2 s2 0 50.0
+Gd2_1 0 s2 p1 0 -8.576444797045295e-07
+Fd2_1 0 s2 V1 -4.288222398522648e-05
+Gr1_2_1 0 s2 x1_a1 0 -1206718015240.3354
+Gr2_re_2_1 0 s2 x2_re_a1 0 382133257433.7156
+Gr2_im_2_1 0 s2 x2_im_a1 0 -388334016128.95905
+Gr3_2_1 0 s2 x3_a1 0 105037000.86241357
+Gr4_2_1 0 s2 x4_a1 0 -3880337681.913899
+Gd2_2 0 s2 p2 0 2.586091448722339e-06
+Fd2_2 0 s2 V2 0.00012930457243611696
+Gr1_2_2 0 s2 x1_a2 0 4626162453731.324
+Gr2_re_2_2 0 s2 x2_re_a2 0 -1236993496269.2827
+Gr2_im_2_2 0 s2 x2_im_a2 0 1636549904038.3657
+Gr3_2_2 0 s2 x3_a2 0 -64448709.071113326
+Gr4_2_2 0 s2 x4_a2 0 -4291322565.3029203
+Gd2_3 0 s2 p3 0 3.824887318505505e-06
+Fd2_3 0 s2 V3 0.00019124436592527527
+Gr1_2_3 0 s2 x1_a3 0 -596016802174.4718
+Gr2_re_2_3 0 s2 x2_re_a3 0 216869254813.08093
+Gr2_im_2_3 0 s2 x2_im_a3 0 -142269732663.1156
+Gr3_2_3 0 s2 x3_a3 0 -58384527.29972925
+Gr4_2_3 0 s2 x4_a3 0 2791616187.8872237
+Gd2_4 0 s2 p4 0 -1.2022001343980904e-06
+Fd2_4 0 s2 V4 -6.0110006719904525e-05
+Gr1_2_4 0 s2 x1_a4 0 1413312421906.588
+Gr2_re_2_4 0 s2 x2_re_a4 0 -1042922876967.3018
+Gr2_im_2_4 0 s2 x2_im_a4 0 -1425676608052.2537
+Gr3_2_4 0 s2 x3_a4 0 143902682.35342407
+Gr4_2_4 0 s2 x4_a4 0 2533655932.350976
+*
+* State networks driven by port 2
+Cx1_a2 x1_a2 0 1.0
+Gx1_a2 0 x1_a2 p2 0 0.07071067811865475
+Fx1_a2 0 x1_a2 V2 3.5355339059327378
+Rp1_a2 0 x1_a2 1.4249470243021733e-13
+Cx2_re_a2 x2_re_a2 0 1.0
+Gx2_re_a2 0 x2_re_a2 p2 0 0.1414213562373095
+Fx2_re_a2 0 x2_re_a2 V2 7.0710678118654755
+Rp2_re_re_a2 0 x2_re_a2 2.2370881216791236e-13
+Gp2_re_im_a2 0 x2_re_a2 x2_im_a2 0 4303319264264.5474
+Cx2_im_a2 x2_im_a2 0 1.0
+Gp2_im_re_a2 0 x2_im_a2 x2_re_a2 0 -4303319264264.5474
+Rp2_im_im_a2 0 x2_im_a2 2.2370881216791236e-13
+Cx3_a2 x3_a2 0 1.0
+Gx3_a2 0 x3_a2 p2 0 0.07071067811865475
+Fx3_a2 0 x3_a2 V2 3.5355339059327378
+Rp3_a2 0 x3_a2 5.911834241884773e-12
+Cx4_a2 x4_a2 0 1.0
+Gx4_a2 0 x4_a2 p2 0 0.07071067811865475
+Fx4_a2 0 x4_a2 V2 3.5355339059327378
+Rp4_a2 0 x4_a2 1.036388375239062e-12
+*
+* Port network for port 3
+V3 p3 s3 0
+R3 s3 0 50.0
+Gd3_1 0 s3 p1 0 -2.2193716536045294e-06
+Fd3_1 0 s3 V1 -0.00011096858268022648
+Gr1_3_1 0 s3 x1_a1 0 1553540072069.103
+Gr2_re_3_1 0 s3 x2_re_a1 0 -1100065293813.306
+Gr2_im_3_1 0 s3 x2_im_a1 0 -1399249300341.87
+Gr3_3_1 0 s3 x3_a1 0 167276704.46165192
+Gr4_3_1 0 s3 x4_a1 0 1657557169.4011416
+Gd3_2 0 s3 p2 0 3.922169743639009e-06
+Fd3_2 0 s3 V2 0.00019610848718195045
+Gr1_3_2 0 s3 x1_a2 0 -563000266004.7948
+Gr2_re_3_2 0 s3 x2_re_a2 0 202310426727.93924
+Gr2_im_3_2 0 s3 x2_im_a2 0 -136086004830.6602
+Gr3_3_2 0 s3 x3_a2 0 -56671503.574542865
+Gr4_3_2 0 s3 x4_a2 0 2835089956.5188394
+Gd3_3 0 s3 p3 0 1.935546855379687e-06
+Fd3_3 0 s3 V3 9.677734276898435e-05
+Gr1_3_3 0 s3 x1_a3 0 -3516392794239.1475
+Gr2_re_3_3 0 s3 x2_re_a3 0 761895075751.6957
+Gr2_im_3_3 0 s3 x2_im_a3 0 -1474122464188.0789
+Gr3_3_3 0 s3 x3_a3 0 -119722457.44307657
+Gr4_3_3 0 s3 x4_a3 0 -3276995993.060734
+Gd3_4 0 s3 p4 0 -4.5248549362406604e-07
+Fd3_4 0 s3 V4 -2.2624274681203302e-05
+Gr1_3_4 0 s3 x1_a4 0 752580231423.9846
+Gr2_re_3_4 0 s3 x2_re_a4 0 -63871572220.253105
+Gr2_im_3_4 0 s3 x2_im_a4 0 405807497842.1717
+Gr3_3_4 0 s3 x3_a4 0 31879208.148758672
+Gr4_3_4 0 s3 x4_a4 0 -1621637280.0329769
+*
+* State networks driven by port 3
+Cx1_a3 x1_a3 0 1.0
+Gx1_a3 0 x1_a3 p3 0 0.07071067811865475
+Fx1_a3 0 x1_a3 V3 3.5355339059327378
+Rp1_a3 0 x1_a3 1.4249470243021733e-13
+Cx2_re_a3 x2_re_a3 0 1.0
+Gx2_re_a3 0 x2_re_a3 p3 0 0.1414213562373095
+Fx2_re_a3 0 x2_re_a3 V3 7.0710678118654755
+Rp2_re_re_a3 0 x2_re_a3 2.2370881216791236e-13
+Gp2_re_im_a3 0 x2_re_a3 x2_im_a3 0 4303319264264.5474
+Cx2_im_a3 x2_im_a3 0 1.0
+Gp2_im_re_a3 0 x2_im_a3 x2_re_a3 0 -4303319264264.5474
+Rp2_im_im_a3 0 x2_im_a3 2.2370881216791236e-13
+Cx3_a3 x3_a3 0 1.0
+Gx3_a3 0 x3_a3 p3 0 0.07071067811865475
+Fx3_a3 0 x3_a3 V3 3.5355339059327378
+Rp3_a3 0 x3_a3 5.911834241884773e-12
+Cx4_a3 x4_a3 0 1.0
+Gx4_a3 0 x4_a3 p3 0 0.07071067811865475
+Fx4_a3 0 x4_a3 V3 3.5355339059327378
+Rp4_a3 0 x4_a3 1.036388375239062e-12
+*
+* Port network for port 4
+V4 p4 s4 0
+R4 s4 0 50.0
+Gd4_1 0 s4 p1 0 3.9136053052706924e-06
+Fd4_1 0 s4 V1 0.00019568026526353463
+Gr1_4_1 0 s4 x1_a1 0 -574644146819.5114
+Gr2_re_4_1 0 s4 x2_re_a1 0 205952059016.52536
+Gr2_im_4_1 0 s4 x2_im_a1 0 -139696145060.85263
+Gr3_4_1 0 s4 x3_a1 0 -56844402.83707588
+Gr4_4_1 0 s4 x4_a1 0 2842833117.266906
+Gd4_2 0 s4 p2 0 -1.3063202438656778e-06
+Fd4_2 0 s4 V2 -6.531601219328388e-05
+Gr1_4_2 0 s4 x1_a2 0 1438174192965.6538
+Gr2_re_4_2 0 s4 x2_re_a2 0 -1061467799029.6914
+Gr2_im_4_2 0 s4 x2_im_a2 0 -1431105778180.4731
+Gr3_4_2 0 s4 x3_a2 0 157695766.38719633
+Gr4_4_2 0 s4 x4_a2 0 2031244531.4579895
+Gd4_3 0 s4 p3 0 -4.4941982827617416e-07
+Fd4_3 0 s4 V3 -2.2470991413808708e-05
+Gr1_4_3 0 s4 x1_a3 0 762460109755.1884
+Gr2_re_4_3 0 s4 x2_re_a3 0 -66345820698.921326
+Gr2_im_4_3 0 s4 x2_im_a3 0 409498495329.96716
+Gr3_4_3 0 s4 x3_a3 0 32645750.97022205
+Gr4_4_3 0 s4 x4_a3 0 -1633618425.3892248
+Gd4_4 0 s4 p4 0 2.1516949479983076e-06
+Fd4_4 0 s4 V4 0.00010758474739991539
+Gr1_4_4 0 s4 x1_a4 0 -3347491311339.526
+Gr2_re_4_4 0 s4 x2_re_a4 0 740210405252.829
+Gr2_im_4_4 0 s4 x2_im_a4 0 -1391048463402.3
+Gr3_4_4 0 s4 x3_a4 0 -100064355.32910477
+Gr4_4_4 0 s4 x4_a4 0 -3835278364.015358
+*
+* State networks driven by port 4
+Cx1_a4 x1_a4 0 1.0
+Gx1_a4 0 x1_a4 p4 0 0.07071067811865475
+Fx1_a4 0 x1_a4 V4 3.5355339059327378
+Rp1_a4 0 x1_a4 1.4249470243021733e-13
+Cx2_re_a4 x2_re_a4 0 1.0
+Gx2_re_a4 0 x2_re_a4 p4 0 0.1414213562373095
+Fx2_re_a4 0 x2_re_a4 V4 7.0710678118654755
+Rp2_re_re_a4 0 x2_re_a4 2.2370881216791236e-13
+Gp2_re_im_a4 0 x2_re_a4 x2_im_a4 0 4303319264264.5474
+Cx2_im_a4 x2_im_a4 0 1.0
+Gp2_im_re_a4 0 x2_im_a4 x2_re_a4 0 -4303319264264.5474
+Rp2_im_im_a4 0 x2_im_a4 2.2370881216791236e-13
+Cx3_a4 x3_a4 0 1.0
+Gx3_a4 0 x3_a4 p4 0 0.07071067811865475
+Fx3_a4 0 x3_a4 V4 3.5355339059327378
+Rp3_a4 0 x3_a4 5.911834241884773e-12
+Cx4_a4 x4_a4 0 1.0
+Gx4_a4 0 x4_a4 p4 0 0.07071067811865475
+Fx4_a4 0 x4_a4 V4 3.5355339059327378
+Rp4_a4 0 x4_a4 1.036388375239062e-12
+.ENDS s_equivalent_0
+
+.SUBCKT BJT_core _net0 _net2 _net1 _net3 
+XBJT_Core _net0 _net2 _net1 _net3 s_equivalent_0 
+.ENDS
+
+IProbe:Pr1 _net0 Collector_voltage
+IProbe:Pr3 _net1 Vout
+Vdc:V1 Vcc gnd U="1.65V"
+.SW:SW3 Sim="HB1" Type="lin" Param="y" Start="0.0005" Stop="0.0035" Points="50"
+R:R5 gnd Vout R="50 Ohm" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+C:C15 _net0 _net1 C="160 fF" V=""
+INDQ:LQ2 Vcc _net0 L="320 pH" Q="13" f="50e9" Mode="Linear" Temp="26.85"
+.HB:HB1 f="50 GHz" n="3" iabstol="1 pA" vabstol="1 uV" reltol="0.001" MaxIter="150"
+C:C13 _net2 _net3 C="100 fF" V=""
+R:R1 _net2 _net3 R="5 kOhm" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+C:C14 _net4 _net5 C="43 fF" V=""
+Iac:I1 _net6 gnd I="y" f="50 GHz" Phase="0" Theta="0" IO="0" TD="0"
+IProbe:Pr2 Vin _net4
+Sub:npn13G3 _net7 _net8 gnd gnd Type="IHP_PDK_nonlinear_components_npn13G2" Nx="10"
+R:R6 _net6 Vin R="50 Ohm" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+Vdc:V3 _net9 gnd U="1.25"
+INDQ:LQ3 _net10 _net9 L="103pH" Q="13" f="50 GHz" Mode="Linear" Temp="26.85"
+Sub:SUB2 _net5 _net2 _net10 Type="T_connection"
+Sub:SUB1 _net3 Collector_voltage _net8 _net7 Type="BJT_core"

modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/Tcon_post_sim.sch

@@ -0,0 +1,97 @@
+<Qucs Schematic 25.1.2>
+<Properties>
+  <View=742,-114,3198,838,1.23109,0,0>
+  <Grid=10,10,1>
+  <DataSet=Tcon_post_sim.dat>
+  <DataDisplay=Tcon_post_sim.dpl>
+  <OpenDisplay=0>
+  <Script=Tcon_post_sim.m>
+  <RunScript=0>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
+<Symbol>
+</Symbol>
+<Components>
+  <IProbe Pr1 1 1940 160 18 -26 1 3>
+  <IProbe Pr3 1 2230 100 -26 16 0 0>
+  <GND * 1 2080 370 0 0 0 0>
+  <Vdc V1 1 2080 320 18 -26 0 1 "1.65V" 1>
+  <GND * 1 2280 280 0 0 0 0>
+  <SpiceLib SpiceLib1 1 2040 -60 -12 16 0 0 "/home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/xyce/models/cornerHBT.lib" 1 "hbt_typ" 1>
+  <R R5 1 2280 190 15 -26 0 1 "50 Ohm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "US" 0>
+  <SpicePar SpicePar1 1 1360 -30 -28 16 0 0 "y=1" 1>
+  <C C15 1 2150 100 -26 17 0 0 "160 fF" 1 "" 0 "neutral" 0>
+  <INDQ LQ2 1 1940 50 -62 -26 0 3 "320 pH" 1 "13" 1 "50e9" 0 "Linear" 0 "26.85" 0>
+  <.HB HB1 1 1460 -50 0 61 0 0 "50 GHz" 0 "3" 1 "1 pA" 0 "1 uV" 0 "0.001" 0 "150" 0>
+  <C C13 1 1720 280 -26 17 0 0 "100 fF" 1 "" 0 "neutral" 0>
+  <R R1 1 1720 210 -26 15 0 0 "5 kOhm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "US" 0>
+  <GND * 1 1220 490 0 0 0 0>
+  <C C14 1 1340 280 -26 17 0 0 "43 fF" 1 "" 0 "neutral" 0>
+  <Iac I1 1 1220 420 20 -26 0 1 "y" 1 "50 GHz" 0 "0" 0 "0" 0 "0" 0 "0" 0>
+  <IProbe Pr2 1 1260 280 -26 16 0 0>
+  <Lib npn13G3 1 1890 460 10 64 0 0 "/home/pedersen/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "10" 1>
+  <GND * 1 1890 510 0 0 0 0>
+  <GND * 1 1920 460 0 0 0 0>
+  <R R6 1 1220 350 15 -26 0 1 "50 Ohm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <Vdc V3 1 1520 600 18 -26 0 1 "1.25" 1>
+  <GND * 1 1520 660 0 0 0 0>
+  <INDQ LQ3 1 1520 520 -62 -26 0 3 "103pH" 1 "13" 1 "50 GHz" 0 "Linear" 0 "26.85" 0>
+  <Sub SUB2 1 1520 300 -26 135 0 0 "../../../../lumped_modelling/em_models_subcircuits/T_conn_subcircuit/T_connection.sch" 0>
+  <Sub SUB1 1 1860 280 -26 155 0 0 "../../../../lumped_modelling/em_models_subcircuits/core_subcircuit/BJT_core.sch" 0>
+  <.SW SW3 1 1180 -40 0 61 0 0 "HB1" 1 "lin" 1 "y" 1 "0.01" 1 "0.05" 1 "50" 1>
+</Components>
+<Wires>
+  <1940 100 1940 130 "" 0 0 0 "">
+  <1940 100 2120 100 "" 0 0 0 "">
+  <2180 100 2200 100 "" 0 0 0 "">
+  <2080 350 2080 370 "" 0 0 0 "">
+  <2080 260 2080 290 "" 0 0 0 "">
+  <2260 100 2280 100 "" 0 0 0 "">
+  <2280 100 2280 160 "" 0 0 0 "">
+  <2280 220 2280 280 "" 0 0 0 "">
+  <1940 80 1940 100 "" 0 0 0 "">
+  <1940 -20 1940 20 "" 0 0 0 "">
+  <1670 280 1690 280 "" 0 0 0 "">
+  <1780 210 1780 280 "" 0 0 0 "">
+  <1750 210 1780 210 "" 0 0 0 "">
+  <1670 210 1670 280 "" 0 0 0 "">
+  <1670 210 1690 210 "" 0 0 0 "">
+  <1220 450 1220 490 "" 0 0 0 "">
+  <1290 280 1310 280 "" 0 0 0 "">
+  <1900 460 1920 460 "" 0 0 0 "">
+  <1830 460 1860 460 "" 0 0 0 "">
+  <1940 190 1940 280 "Collector_voltage" 1970 170 24 "">
+  <1220 280 1230 280 "" 0 0 0 "">
+  <1220 280 1220 320 "" 0 0 0 "">
+  <1220 380 1220 390 "" 0 0 0 "">
+  <1520 630 1520 660 "" 0 0 0 "">
+  <1520 370 1520 490 "" 0 0 0 "">
+  <1520 550 1520 570 "" 0 0 0 "">
+  <1930 280 1940 280 "" 0 0 0 "">
+  <1830 360 1830 460 "" 0 0 0 "">
+  <1890 360 1890 410 "" 0 0 0 "">
+  <1750 280 1780 280 "" 0 0 0 "">
+  <1780 280 1800 280 "" 0 0 0 "">
+  <1370 280 1410 280 "" 0 0 0 "">
+  <1630 280 1670 280 "" 0 0 0 "">
+  <2080 260 2080 260 "Vcc" 2110 230 0 "">
+  <2280 100 2280 100 "Vout" 2300 40 0 "">
+  <1940 -20 1940 -20 "Vcc" 1970 -50 0 "">
+  <1220 280 1220 280 "Vin" 1170 240 0 "">
+</Wires>
+<Diagrams>
+  <Rect 2410 379 351 279 3 #c0c0c0 1 00 1 -2.5e+11 1e+11 2.5e+11 1 -0.00102131 0.002 0.0112344 1 -1 0.5 1 315 0 225 1 0 0 "" "" "">
+	<"xyce/V(VOUT)" #0000ff 0 3 0 0 0>
+	<"xyce/V(VIN)" #ff0000 0 3 0 0 0>
+  </Rect>
+  <Rect 2400 729 351 279 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
+	<"xyce/I(PR2)" #0000ff 0 3 0 0 0>
+	<"xyce/I(PR3)" #ff0000 0 3 0 0 0>
+  </Rect>
+</Diagrams>
+<Paintings>
+</Paintings>

modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/csv/IPR2.csv

@@ -0,0 +1,43 @@
+"FREQ";"r xyce/I(PR2)";"i xyce/I(PR2)"
+-1.5e+11;8.15879e-21;1.46448e-20
+-1e+11;-6.5348e-21;3.03306e-20
+-5e+10;-1.98267e-20;0.00025
+0;-7.20495e-19;0
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+1e+11;-6.5348e-21;-3.03306e-20
+1.5e+11;8.15879e-21;-1.46448e-20
+-1.5e+11;2.53535e-20;4.16749e-20
+-1e+11;-2.05374e-20;3.98265e-20
+-5e+10;-3.29053e-20;0.000285714
+0;-1.2613e-19;0
+5e+10;-3.29053e-20;-0.000285714
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+1.5e+11;2.53535e-20;-4.16749e-20
+-1.5e+11;3.9697e-20;3.18093e-20
+-1e+11;3.11027e-21;4.46909e-20
+-5e+10;-3.49178e-20;0.000321429
+0;4.2261e-19;0
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+1e+11;3.11027e-21;-4.46909e-20
+1.5e+11;3.9697e-20;-3.18093e-20
+-1.5e+11;1.71161e-20;-8.97756e-21
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modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/csv/IPR3.csv

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modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/csv/Vin.csv

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modules/module_2_50GHz_MPA/part_4_layout_EMsims/em_components/T_connection_2/post_layout_sim/schematic/csv/Vout.csv

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