create subfolders for layout

2024-12-17 11:53:23 +01:00 · 2024-12-17 11:53:23 +01:00 · 6fbf7a0381
parent 311e151c3a
commit 6fbf7a0381
6 changed files with 651 additions and 0 deletions
--- a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch
+++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/schematic_mod/two_stage_OTA_layout.sch
@ -0,0 +1,411 @@
+v {xschem version=3.4.5 file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 450 -435 450 -395 {
+lab=dn3}
+N 450 -435 560 -435 {
+lab=dn3}
+N 660 -305 860 -305 {
+lab=vss}
+N 560 -365 620 -365 {
+lab=dn3}
+N 560 -435 560 -365 {
+lab=dn3}
+N 490 -365 560 -365 {
+lab=dn3}
+N 450 -495 450 -435 {
+lab=dn3}
+N 450 -525 660 -525 {
+lab=well}
+N 450 -575 450 -555 {
+lab=dn2}
+N 660 -575 660 -555 {
+lab=dn2}
+N 560 -575 660 -575 {
+lab=dn2}
+N 380 -525 410 -525 {
+lab=v-}
+N 700 -525 730 -525 {
+lab=v+}
+N 390 -625 520 -625 {
+lab=iout}
+N 170 -575 170 -555 {
+lab=iout}
+N 170 -575 220 -575 {
+lab=iout}
+N 220 -625 240 -625 {
+lab=iout}
+N 170 -595 170 -575 {
+lab=iout}
+N 220 -625 220 -575 {
+lab=iout}
+N 210 -625 220 -625 {
+lab=iout}
+N 800 -625 820 -625 {
+lab=iout}
+N 860 -525 900 -525 {
+lab=vout}
+N 860 -595 860 -525 {
+lab=vout}
+N 660 -400 660 -395 {
+lab=dn4}
+N 560 -675 860 -675 {
+lab=vdd}
+N 560 -595 560 -575 {
+lab=dn2}
+N 450 -575 560 -575 {
+lab=dn2}
+N 760 -400 820 -400 {
+lab=dn4}
+N 660 -495 660 -400 {
+lab=dn4}
+N 760 -460 760 -400 {
+lab=dn4}
+N 660 -400 760 -400 {
+lab=dn4}
+N 860 -460 860 -430 {
+lab=vout}
+N 820 -460 860 -460 {
+lab=vout}
+N 860 -525 860 -460 {
+lab=vout}
+N 230 -285 285 -285 {
+lab=well}
+N 190 -315 190 -285 {
+lab=vdd}
+N 230 -255 230 -235 {
+lab=dn4}
+N 75 -285 130 -285 {
+lab=well}
+N 35 -315 35 -285 {
+lab=vdd}
+N 75 -255 75 -235 {
+lab=dn3}
+N 620 -225 620 -175 {
+lab=vss}
+N 620 -175 660 -175 {
+lab=vss}
+N 410 -230 410 -180 {
+lab=vss}
+N 410 -180 450 -180 {
+lab=vss}
+N 660 -335 660 -305 {
+lab=vss}
+N 450 -305 660 -305 {
+lab=vss}
+N 450 -335 450 -305 {
+lab=vss}
+N 370 -365 450 -365 {
+lab=sub!}
+N 660 -365 740 -365 {
+lab=sub!}
+N 860 -375 860 -305 {
+lab=vss}
+N 1115 -355 1175 -355 {
+lab=sub!}
+N 1115 -385 1115 -355 {
+lab=sub!}
+N 1055 -355 1115 -355 {
+lab=sub!}
+N 1055 -295 1055 -275 {
+lab=vss}
+N 1115 -275 1175 -275 {
+lab=vss}
+N 1175 -295 1175 -275 {
+lab=vss}
+N 1115 -275 1115 -255 {
+lab=vss}
+N 1055 -275 1115 -275 {
+lab=vss}
+N 450 -200 450 -180 {
+lab=vss}
+N 660 -195 660 -175 {
+lab=vss}
+N 860 -400 940 -400 {
+lab=sub!}
+N 450 -230 515 -230 {
+lab=sub!}
+N 660 -225 725 -225 {
+lab=sub!}
+N 190 -315 230 -315 {
+lab=vdd}
+N 35 -315 75 -315 {
+lab=vdd}
+N 1290 -385 1290 -355 {
+lab=well}
+N 1290 -295 1290 -255 {
+lab=vdd}
+N 860 -675 860 -655 {
+lab=vdd}
+N 170 -675 170 -655 {
+lab=vdd}
+N 1370 -385 1370 -355 {
+lab=well1}
+N 1370 -295 1370 -255 {
+lab=vdd}
+N 105 -625 170 -625 {
+lab=well1}
+N 860 -625 930 -625 {
+lab=well1}
+N 1455 -385 1455 -355 {
+lab=well2}
+N 1455 -295 1455 -255 {
+lab=vdd}
+N 560 -675 560 -655 {
+lab=vdd}
+N 170 -675 560 -675 {
+lab=vdd}
+N 560 -625 630 -625 {
+lab=well2}
+N 520 -755 560 -755 {
+lab=vdd}
+N 520 -755 520 -725 {
+lab=vdd}
+N 560 -695 560 -675 {
+lab=vdd}
+N 560 -725 615 -725 {
+lab=well2}
+N 720 -795 760 -795 {
+lab=vdd}
+N 720 -795 720 -765 {
+lab=vdd}
+N 760 -735 760 -715 {
+lab=dn2}
+N 760 -765 815 -765 {
+lab=well2}
+N 230 -395 285 -395 {
+lab=well}
+N 190 -425 190 -395 {
+lab=vdd}
+N 230 -365 230 -345 {
+lab=dn2}
+N 75 -395 130 -395 {
+lab=well}
+N 35 -425 35 -395 {
+lab=vdd}
+N 75 -365 75 -345 {
+lab=dn2}
+N 190 -425 230 -425 {
+lab=vdd}
+N 35 -425 75 -425 {
+lab=vdd}
+N 660 -305 660 -255 {
+lab=vss}
+N 450 -305 450 -260 {
+lab=vss}
+C {sg13g2_pr/sg13_lv_nmos.sym} 640 -365 2 1 {name=M4
+l=9.75u
+w=720n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_nmos.sym} 470 -365 2 0 {name=M3
+l=9.75u
+w=720n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 680 -525 0 1 {name=M2
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 540 -625 0 0 {name=M5
+l=1.95u
+w=5.3u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 840 -625 0 0 {name=M7
+l=2.08u
+w=75u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_nmos.sym} 840 -400 2 1 {name=M6
+l=9.75u
+w=28.8u
+ng=4
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-}
+C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+}
+C {iopin.sym} 560 -305 1 1 {name=p5 lab=vss}
+C {iopin.sym} 455 -675 1 1 {name=p1 lab=vdd}
+C {iopin.sym} 170 -555 0 1 {name=p3 lab=iout}
+C {iopin.sym} 900 -525 0 0 {name=p8 lab=vout}
+C {lab_pin.sym} 240 -625 0 1 {name=p7 sig_type=std_logic lab=iout}
+C {lab_pin.sym} 800 -625 0 0 {name=p6 sig_type=std_logic lab=iout}
+C {sg13g2_pr/sg13_lv_pmos.sym} 190 -625 0 1 {name=M9
+l=2.08u
+w=75u
+ng=8
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/cap_cmim.sym} 790 -460 3 0 {name=C2
+model=cap_cmim
+w=22.295e-6
+l=22.295e-6
+m=1
+spiceprefix=X}
+C {lab_pin.sym} 390 -625 0 0 {name=p4 sig_type=std_logic lab=iout}
+C {lab_pin.sym} 450 -455 0 0 {name=p9 sig_type=std_logic lab=dn3}
+C {lab_pin.sym} 660 -455 0 0 {name=p12 sig_type=std_logic lab=dn4}
+C {sg13g2_pr/sg13_lv_pmos.sym} 210 -285 0 0 {name=M8
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 190 -315 0 0 {name=p15 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/sg13_lv_pmos.sym} 55 -285 0 0 {name=M10
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 35 -315 0 0 {name=p17 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/sg13_lv_nmos.sym} 640 -225 2 1 {name=M11
+l=9.75u
+w=720n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {lab_pin.sym} 660 -175 2 0 {name=p19 sig_type=std_logic lab=vss}
+C {sg13g2_pr/sg13_lv_nmos.sym} 430 -230 2 1 {name=M12
+l=9.75u
+w=720n
+ng=1
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {lab_pin.sym} 450 -180 2 0 {name=p21 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1115 -385 0 0 {name=p23 sig_type=std_logic lab=sub!}
+C {lab_pin.sym} 1115 -255 2 0 {name=p24 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 740 -365 0 1 {name=p25 sig_type=std_logic lab=sub!}
+C {lab_pin.sym} 370 -365 0 0 {name=p26 sig_type=std_logic lab=sub!}
+C {lab_pin.sym} 940 -400 0 1 {name=p27 sig_type=std_logic lab=sub!}
+C {sg13g2_pr/ptap1.sym} 1055 -325 2 0 {name=R1
+model=ptap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {sg13g2_pr/ptap1.sym} 1175 -325 2 0 {name=R2
+model=ptap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {lab_pin.sym} 515 -230 0 1 {name=p28 sig_type=std_logic lab=sub!}
+C {lab_pin.sym} 725 -225 0 1 {name=p29 sig_type=std_logic lab=sub!}
+C {lab_pin.sym} 1290 -385 0 0 {name=p30 sig_type=std_logic lab=well}
+C {lab_pin.sym} 1290 -255 0 0 {name=p31 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/ntap1.sym} 1290 -325 2 0 {name=R3
+model=ntap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {lab_pin.sym} 560 -525 3 0 {name=p2 sig_type=std_logic lab=well}
+C {lab_pin.sym} 130 -285 0 1 {name=p32 sig_type=std_logic lab=well}
+C {lab_pin.sym} 285 -285 0 1 {name=p33 sig_type=std_logic lab=well}
+C {lab_pin.sym} 1370 -385 0 0 {name=p34 sig_type=std_logic lab=well1}
+C {lab_pin.sym} 1370 -255 0 0 {name=p35 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/ntap1.sym} 1370 -325 2 0 {name=R4
+model=ntap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {lab_pin.sym} 105 -625 0 0 {name=p36 sig_type=std_logic lab=well1}
+C {lab_pin.sym} 930 -625 2 0 {name=p37 sig_type=std_logic lab=well1}
+C {lab_pin.sym} 1455 -385 0 0 {name=p38 sig_type=std_logic lab=well2}
+C {lab_pin.sym} 1455 -255 0 0 {name=p39 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/ntap1.sym} 1455 -325 2 0 {name=R5
+model=ntap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {lab_pin.sym} 560 -585 0 1 {name=p40 sig_type=std_logic lab=dn2}
+C {lab_pin.sym} 630 -625 2 0 {name=p41 sig_type=std_logic lab=well2}
+C {lab_pin.sym} 75 -235 0 0 {name=p43 sig_type=std_logic lab=dn3}
+C {lab_pin.sym} 230 -235 0 0 {name=p18 sig_type=std_logic lab=dn4}
+C {sg13g2_pr/sg13_lv_pmos.sym} 540 -725 0 0 {name=M13
+l=1.95u
+w=5.3u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 520 -755 0 0 {name=p22 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 615 -725 2 0 {name=p45 sig_type=std_logic lab=well2}
+C {sg13g2_pr/sg13_lv_pmos.sym} 740 -765 0 0 {name=M14
+l=1.95u
+w=5.3u
+ng=1
+m=1
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 720 -795 0 0 {name=p46 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 760 -715 0 0 {name=p47 sig_type=std_logic lab=dn2}
+C {lab_pin.sym} 815 -765 2 0 {name=p48 sig_type=std_logic lab=well2}
+C {sg13g2_pr/sg13_lv_pmos.sym} 210 -395 0 0 {name=M15
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 190 -425 0 0 {name=p49 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/sg13_lv_pmos.sym} 55 -395 0 0 {name=M16
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 35 -425 0 0 {name=p50 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 130 -395 0 1 {name=p51 sig_type=std_logic lab=well}
+C {lab_pin.sym} 285 -395 0 1 {name=p52 sig_type=std_logic lab=well}
+C {lab_pin.sym} 75 -345 0 0 {name=p53 sig_type=std_logic lab=dn2}
+C {lab_pin.sym} 230 -345 0 0 {name=p54 sig_type=std_logic lab=dn2}
--- a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA.gds
+++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA.gds
--- a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout_extracted.cir
+++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/full_OTA/two_stage_OTA_layout_extracted.cir
@ -0,0 +1,75 @@
+* Extracted by KLayout with SG13G2 LVS runset on : 13/12/2024 15:39
+
+.SUBCKT two_stage_OTA_layout
+M$1 \$2 \$70 \$3 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=2.448p AD=1.368p PS=15.08u
+ PD=7.58u
+M$2 \$3 \$73 \$4 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=1.368p AD=1.368p PS=7.58u
+ PD=7.58u
+M$3 \$4 \$8 \$5 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=1.368p AD=1.368p PS=7.58u
+ PD=7.58u
+M$4 \$5 \$8 \$6 \$1 sg13_lv_nmos L=9.75u W=7.2u AS=1.368p AD=2.448p PS=7.58u
+ PD=15.08u
+M$5 \$9 \$70 \$10 \$69 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$6 \$11 \$70 \$12 \$71 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$7 \$13 \$73 \$14 \$72 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$8 \$15 \$73 \$16 \$74 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$9 \$37 \$86 \$38 \$85 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$10 \$39 \$88 \$40 \$87 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$11 \$41 \$91 \$42 \$90 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$12 \$43 \$93 \$44 \$92 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$13 \$49 \$83 \$50 \$82 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$14 \$51 \$81 \$52 \$80 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$15 \$53 \$79 \$54 \$78 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$16 \$55 \$76 \$56 \$77 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$17 \$17 \$8 \$18 \$94 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
+ PS=11.28u PD=11.28u
+M$18 \$45 \$98 \$46 \$99 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
+ PS=11.28u PD=11.28u
+M$19 \$47 \$95 \$48 \$97 sg13_lv_pmos L=1.95u W=5.3u AS=1.802p AD=1.802p
+ PS=11.28u PD=11.28u
+M$20 \$19 \$8 \$20 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=3.1875p AD=1.78125p
+ PS=19.43u PD=9.755u
+M$21 \$20 \$8 \$21 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
+ PS=9.755u PD=9.755u
+M$22 \$21 \$8 \$22 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
+ PS=9.755u PD=9.755u
+M$23 \$22 \$8 \$23 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
+ PS=9.755u PD=9.755u
+M$24 \$23 \$8 \$24 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
+ PS=9.755u PD=9.755u
+M$25 \$24 \$8 \$25 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
+ PS=9.755u PD=9.755u
+M$26 \$25 \$8 \$26 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=1.78125p
+ PS=9.755u PD=9.755u
+M$27 \$26 \$106 \$27 \$108 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=3.1875p
+ PS=9.755u PD=19.43u
+M$28 \$28 \$107 \$29 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=3.1875p AD=1.78125p
+ PS=19.43u PD=9.755u
+M$29 \$29 \$110 \$30 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
+ AD=1.78125p PS=9.755u PD=9.755u
+M$30 \$30 \$109 \$31 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
+ AD=1.78125p PS=9.755u PD=9.755u
+M$31 \$31 \$111 \$32 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
+ AD=1.78125p PS=9.755u PD=9.755u
+M$32 \$32 \$112 \$33 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
+ AD=1.78125p PS=9.755u PD=9.755u
+M$33 \$33 \$113 \$34 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
+ AD=1.78125p PS=9.755u PD=9.755u
+M$34 \$34 \$105 \$35 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p
+ AD=1.78125p PS=9.755u PD=9.755u
+M$35 \$35 \$103 \$36 \$104 sg13_lv_pmos L=2.08u W=9.375u AS=1.78125p AD=3.1875p
+ PS=9.755u PD=19.43u
+C$36 \$102 \$101 cap_cmim w=22.295u l=22.295u A=497.067025p P=89.18u m=1
+.ENDS two_stage_OTA_layout
--- a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid.gds
+++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid.gds
--- a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid_extracted.cir
+++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid_extracted.cir
@ -0,0 +1,28 @@
+* Extracted by KLayout with SG13G2 LVS runset on : 16/12/2024 11:10
+
+.SUBCKT input_common_centroid
+M$1 \$2 \$31 \$3 \$37 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$2 \$3 \$32 \$4 \$37 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$3 \$4 \$34 \$5 \$37 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$4 \$6 \$36 \$7 \$33 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$5 \$7 \$35 \$8 \$33 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$6 \$8 \$30 \$9 \$33 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$7 \$22 \$50 \$23 \$53 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$8 \$23 \$51 \$24 \$53 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$9 \$24 \$52 \$25 \$53 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$10 \$26 \$54 \$27 \$56 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$11 \$27 \$55 \$28 \$56 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+M$12 \$28 \$57 \$29 \$56 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
+.ENDS input_common_centroid
--- a/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch
+++ b/modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch
@ -0,0 +1,137 @@
+v {xschem version=3.4.5 file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 450 -495 450 -395 {
+lab=dn3}
+N 450 -525 660 -525 {
+lab=well}
+N 450 -575 450 -555 {
+lab=dn2}
+N 660 -575 660 -555 {
+lab=dn2}
+N 560 -575 660 -575 {
+lab=dn2}
+N 380 -525 410 -525 {
+lab=v-}
+N 700 -525 730 -525 {
+lab=v+}
+N 560 -595 560 -575 {
+lab=dn2}
+N 450 -575 560 -575 {
+lab=dn2}
+N 660 -495 660 -400 {
+lab=dn4}
+N 230 -285 285 -285 {
+lab=well}
+N 190 -315 190 -285 {
+lab=vdd}
+N 230 -255 230 -235 {
+lab=dn4}
+N 75 -285 130 -285 {
+lab=well}
+N 35 -315 35 -285 {
+lab=vdd}
+N 75 -255 75 -235 {
+lab=dn3}
+N 190 -315 230 -315 {
+lab=vdd}
+N 35 -315 75 -315 {
+lab=vdd}
+N 560 -445 560 -415 {
+lab=well}
+N 560 -355 560 -315 {
+lab=#net1}
+N 230 -395 285 -395 {
+lab=well}
+N 190 -425 190 -395 {
+lab=vdd}
+N 230 -365 230 -345 {
+lab=dn2}
+N 75 -395 130 -395 {
+lab=well}
+N 35 -425 35 -395 {
+lab=vdd}
+N 75 -365 75 -345 {
+lab=dn2}
+N 190 -425 230 -425 {
+lab=vdd}
+N 35 -425 75 -425 {
+lab=vdd}
+C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_pmos.sym} 680 -525 0 1 {name=M2
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-}
+C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+}
+C {iopin.sym} 560 -315 2 1 {name=p1 lab=vdd}
+C {lab_pin.sym} 450 -455 0 0 {name=p9 sig_type=std_logic lab=dn3}
+C {lab_pin.sym} 660 -455 0 0 {name=p12 sig_type=std_logic lab=dn4}
+C {sg13g2_pr/sg13_lv_pmos.sym} 210 -285 0 0 {name=M8
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 190 -315 0 0 {name=p15 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/sg13_lv_pmos.sym} 55 -285 0 0 {name=M10
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 35 -315 0 0 {name=p17 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 560 -445 0 0 {name=p30 sig_type=std_logic lab=well}
+C {sg13g2_pr/ntap1.sym} 560 -385 2 0 {name=R3
+model=ntap1
+spiceprefix=X
+R=262.847.0
+Imax=0.3e-6
+}
+C {lab_pin.sym} 560 -525 3 0 {name=p2 sig_type=std_logic lab=well}
+C {lab_pin.sym} 130 -285 0 1 {name=p32 sig_type=std_logic lab=well}
+C {lab_pin.sym} 285 -285 0 1 {name=p33 sig_type=std_logic lab=well}
+C {lab_pin.sym} 560 -585 0 1 {name=p40 sig_type=std_logic lab=dn2}
+C {lab_pin.sym} 75 -235 0 0 {name=p43 sig_type=std_logic lab=dn3}
+C {lab_pin.sym} 230 -235 0 0 {name=p18 sig_type=std_logic lab=dn4}
+C {sg13g2_pr/sg13_lv_pmos.sym} 210 -395 0 0 {name=M15
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 190 -425 0 0 {name=p49 sig_type=std_logic lab=vdd}
+C {sg13g2_pr/sg13_lv_pmos.sym} 55 -395 0 0 {name=M16
+l=3.7u
+w=3.64u
+ng=1
+m=2
+model=sg13_lv_pmos
+spiceprefix=X
+}
+C {lab_pin.sym} 35 -425 0 0 {name=p50 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 130 -395 0 1 {name=p51 sig_type=std_logic lab=well}
+C {lab_pin.sym} 285 -395 0 1 {name=p52 sig_type=std_logic lab=well}
+C {lab_pin.sym} 75 -345 0 0 {name=p53 sig_type=std_logic lab=dn2}
+C {lab_pin.sym} 230 -345 0 0 {name=p54 sig_type=std_logic lab=dn2}