ignore spice
This commit is contained in:
PhillipRambo
parent
504c431f7c
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6c3fb8a2b6
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**/.vscode/
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**/.vscode/
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**/.ipynb_checkpoints/
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**/.ipynb_checkpoints/
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*.raw
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*.raw
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*.spice
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** OTA_SIMPLE flat netlist
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*.PININFO V-:B V+:B VSS:B VDD:B IOUT:B VOUT:B
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M4 NET3 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
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M3 NET1 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
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M1 NET1 V- NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
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M2 NET3 V+ NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
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M5 NET2 IOUT VDD VDD SG13_LV_PMOS L=1.95U W=5.3U NG=1 M=1
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M7 VOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
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M6 VOUT NET3 VSS VSS SG13_LV_NMOS L=9.75U W=28.8U NG=4 M=1
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M9 IOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
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C2 NET3 VOUT CAP_CMIM W=22.295E-6 L=22.295E-6 M=1
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.end
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** OTA_SIMPLE flat netlist
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*.PININFO V-:B V+:B VSS:B VDD:B IOUT:B VOUT:B
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M4 NET3 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
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M3 NET1 NET1 VSS VSS SG13_LV_NMOS L=9.75U W=720N NG=1 M=1
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M1 NET1 V- NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
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M2 NET3 V+ NET2 VDD SG13_LV_PMOS L=3.64U W=7.41U NG=1 M=1
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M5 NET2 IOUT VDD VDD SG13_LV_PMOS L=1.95U W=5.3U NG=1 M=1
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M7 VOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
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M6 VOUT NET3 VSS VSS SG13_LV_NMOS L=9.75U W=28.8U NG=4 M=1
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M9 IOUT IOUT VDD VDD SG13_LV_PMOS L=2.08U W=75U NG=8 M=1
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C2 NET3 VOUT CAP_CMIM W=22.295E-6 L=22.295E-6 M=1
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.end
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/ota_testbench.sch
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**.subckt ota_testbench vout vout1 vout2
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*.iopin vout
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*.iopin vout1
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*.iopin vout2
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x1 vdd net1 vp vm vout GND two_stage_OTA
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V1 vp GND DC 0.6 AC 1 0
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VDD vdd GND DC 1.2
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I0 net1 GND 80u
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Cload vout GND 500f m=1
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L6 vout vm 4G m=1
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C1 vm GND 4G m=1
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x2 vdd net2 vp vp vout1 GND two_stage_OTA
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I1 net2 GND 80u
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Cload1 vout1 GND 500f m=1
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x3 VDDac net3 net4 vm vout2 GND two_stage_OTA
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I2 net3 GND 80u
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L13 vout2 vm 4G m=1
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C2 vm GND 4G m=1
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V2 VDDac GND DC 1.2 AC 1 0
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V4 net4 GND DC 0.6
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**** begin user architecture code
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.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ
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.lib cornerMOSlv.lib mos_tt
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.control
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op
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save all
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write tb_OTA_op.raw
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.endc
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.control
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op
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ac dec 100 1 10e6
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save all
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let Av = db(v(vout))
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let PSRR = db(v(vout2)/v(VDDac))
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let CMRR = db((v(vout)/v(vp))/(v(vout1)/v(vp)))
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let phase = 180*cph(vout)/pi
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write output_file.raw
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.endc
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**** end user architecture code
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**.ends
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* expanding symbol: two_stage_OTA.sym # of pins=6
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** sym_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym
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** sch_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
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.subckt two_stage_OTA vdd iout v+ v- vout vss
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*.iopin v-
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*.iopin v+
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*.iopin vss
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*.iopin vdd
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*.iopin iout
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*.iopin vout
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XM4 net3 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
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XM3 net1 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
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XM1 net1 v- net2 vdd sg13_lv_pmos w=7.41u l=3.64u ng=1 m=1
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XM2 net3 v+ net2 vdd sg13_lv_pmos w=7.41u l=3.64u ng=1 m=1
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XM5 net2 iout vdd vdd sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1
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XM7 vout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
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XM6 vout net3 vss vss sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1
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XM9 iout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
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XC2 net3 vout cap_cmim w=22.295e-6 l=22.295e-6 m=1
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.ends
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.GLOBAL GND
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.end
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