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modules/module_1_bandgap_reference/part_3_layout/layout_tutorial.md
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# Layout and Physical Verification C# Layout and Physical Verification
In this tutorial, we will guide you through the systematic process of laying out the bandgap reference circuit. This task is divided into two parts: the design of the two-stage OTA and the bandgap core, both of which were created in parts 1 and 2 of this series. The primary focus here is to transition the design from the schematic editor into KLayout for layout implementation, ensuring that pycells are correctly utilized in the layout process. In this tutorial, we will guide you through the systematic process of laying out the bandgap reference circuit. This task is divided into two parts: the design of the two-stage OTA and the bandgap core, both of which were created in parts 1 and 2 of this series. The primary focus here is to transition the design from the schematic editor into KLayout for layout implementation, ensuring that pycells are correctly utilized in the layout process.
@ -90,7 +90,7 @@ As we move into the layout phase, performing LVS (Layout vs. Schematic) checks i
- Enable the option **LVS netlist: Top level is a .subckt**. - Enable the option **LVS netlist: Top level is a .subckt**.
- Click **Netlist** to generate the required file. - Click **Netlist** to generate the required file.
2. **Inspect the CDL File**: 2. **Inspect the spice File**:
- Open the `.spice` file in a text editor to ensure its contents look correct. You should see something like this: - Open the `.spice` file in a text editor to ensure its contents look correct. You should see something like this: