Update pex.md
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Test
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Parasitic Extraction (PEX)
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Parasitic extraction is an important step in the analog design flow, kind of like EM simulation. After you finish the physical layout, this step analyzes how unintended parasitic resistances and capacitances affect your circuit’s behavior.
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For this workflow, we use the kpex tool developed by [Martin Jan Köhler](https://github.com/martinjankoehler), which is open-source and integrates well with KLayout. You can find it here: [klayout-pex](https://github.com/martinjankoehler/klayout-pex). Big thanks to Martin for sharing this tool!
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You can check out installation instructions directly on the repo or the official website: [official website](https://martinjankoehler.github.io/klayout-pex-website/).
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## Basic Commands
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Once installed, run:
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```bash
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kpex --help
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```
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From this we see that we have lots of infomration we can specify to `kpex`. As it can be seen there is a lot of different configuration options depending on your use case, lets dive into this simple example:
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```
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kpex \
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--pdk ihp_sg13g2 \
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--gds design.gds \
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--schematic design.spice \
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--cell top \
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--magic \
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--magic_mode RC \
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--out_dir output/
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```
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🔧 Explanation of each option:
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--pdk ihp_sg13g2
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Specifies the process design kit to use. In this case, the IHP SG13G2 PDK.
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--gds design.gds
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Path to the GDS layout file for the design.
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--schematic design.spice
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Path to the SPICE netlist of the schematic used for LVS comparison.
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--cell top
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Specifies the top-level cell name in the GDS file to extract parasitics from.
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--magic
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Tells kpex to use Magic’s parasitic extraction engine (alternatives: `--fastercap`, `--2.5D`, `--fastcap`).
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--magic_mode RC
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Specifies the extraction mode used by Magic. Can be:
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- `CC` – extract only capacitances
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- `RC` – extract resistances and capacitances (default)
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- `R` – extract only resistances
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--mode RC
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If using `--2.5D` instead of `--magic`, use `--mode` to specify the extraction mode. Same options apply: `CC`, `RC`, or `R`.
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--out_dir output/
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Output directory where results (LVS database, parasitic netlist, logs) will be saved.
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This can simply be tried out with a gds file to confirm everthing is working
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## What will it create?
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Taking a very basic inverter example we will start by viewing the netlist from xschem seen here
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```
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.SUBCKT inverter Vdd Vin Vout Gnd
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*.PININFO Vout:B Vdd:B Vin:B Gnd:B
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M1 Gnd Vin Vout net2 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
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M2 Vout Vin Vdd net1 sg13_lv_pmos w=2.0u l=0.45u ng=1 m=1
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R1 Vdd net1 ntap1 A=6.084e-13 P=3.12e-06
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R2 Gnd net2 ptap1 A=6.084e-13 P=3.12e-06
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.ENDS
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```
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as it can be seen its a very simple netlist with two transistors and tap devices. We have the parameters describing the instace parameters and thats it. Using the flow explained above a simple GDS layout has been made and can be seen below:
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<p align="center">
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<img src="../.media/inverter_layout.png" width="400" height="450" />
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</p>
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for this layout a simple shell script has been made in order to execute the kpex. This i seen below
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```
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#!/bin/bash
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set -e
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# Hardcoded paths (except PDK stuff)
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PYTHON_ENV="/home/pedersen/misc/klayout_pex/bin/activate"
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KPEX_MAGIC_EXE="/home/pedersen/.local/bin/magic"
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LAYOUT_PATH="../layout/inverter.gds"
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SCHEMATIC="../simulations/inverter.spice"
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PDK_NAME="ihp_sg13g2"
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MAGICRC="$PDK_ROOT/$PDK_NAME/libs.tech/magic/ihp-sg13g2.magicrc"
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# Activate Python environment
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source "$PYTHON_ENV"
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# Run parasitic extraction with kpex
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kpex \
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--pdk "$PDK_NAME" \
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--magic \
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--schematic "$SCHEMATIC" \
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--gds "$LAYOUT_PATH" \
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--magicrc "$MAGICRC" \
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--magic_mode RC \
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--magic_cthresh 0.02 \
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--magic_rthresh 50 \
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--magic_short resistor \
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--magic_merge conservative \
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--out_dir /.pex_output
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```
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### Script Explanation
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This bash script automates parasitic extraction using **kpex** with the IHP SG13G2 PDK. Here's what each part does:
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- `set -e`
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Ensures the script exits immediately if any command fails, preventing cascading errors.
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- **paths:**
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- `PYTHON_ENV`: Path to the Python virtual environment of klayout-pex (optional depending on your setup).
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- `KPEX_MAGIC_EXE`: Path to the Magic engine executable.
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- `LAYOUT_PATH`: Relative path to the layout GDS file to extract parasitics from.
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- `SCHEMATIC`: Relative path to the SPICE netlist schematic used for LVS and parasitic extraction (Top level must be a subcircuit! to be compatible with costum python script later! Refer to LVS guide in klayout)
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- `PDK_NAME` and `MAGICRC`:
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- `PDK_NAME` specifies the Process Design Kit to use (`ihp_sg13g2`).
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- `MAGICRC` points to the Magic configuration file for the PDK
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(this should be already setup if you followed installation of the IHP open PDK)
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- `source "$PYTHON_ENV"`:
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Activates the Python environment so the `kpex` command and dependencies run properly.
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- The `kpex` command runs parasitic extraction with these options:
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- `--pdk`: Selects the PDK.
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- `--magic`: Uses Magic’s extraction engine.
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- `--schematic`: Specifies the schematic netlist for LVS comparison and annotation.
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- `--gds`: Layout file to extract from.
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- `--magicrc`: PDK-specific Magic configuration file.
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- `--magic_mode RC`: Extraction mode producing both resistive and capacitive parasitics.
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- `--magic_cthresh 0.02`: Capacitance extraction threshold (farads).
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- `--magic_rthresh 50`: Resistance extraction threshold (ohms).
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- `--magic_short resistor`: Method to handle shorts using resistors.
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- `--magic_merge conservative`: Merging style to combine parasitics cautiously.
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- `--out_dir ./pex_output`: Directory where extraction results (parasitic netlists, logs) are saved.
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---
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Once the script has been run, a log is printed and a folder is generated containing the results:
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```
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.
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└── inverter__inverter
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├── inverter_dummy_schematic.spice
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├── kpex.log
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├── kpex_plain.log
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└── magic_RC
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├── inverter.ext
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├── inverter_MAGIC_RC_Output.txt
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├── inverter_MAGIC_RC_Script.tcl
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├── inverter_MAGIC_report.rdb.gz
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├── inverter.pex.spice
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└── inverter.res.ext
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```
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Among the outputs, the important file is `inverter.pex.spice`, shown below:
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```
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* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
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.subckt inverter_pex Vdd Vin Vout Gnd
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X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
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X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
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C0 Vout Vin 0.10077f
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C1 Vin Vdd 0.14482f
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C2 Vout Vdd 0.13155f
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R0 Vin Vin.n0 7.52248
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C3 Vout Gnd 0.39245f
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C4 Vin Gnd 0.64666f
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C5 Vdd Gnd 0.15308f
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.ends
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```
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As can be seen, it's the same netlist structure as shown earlier but now with parasitics inserted.
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- The `X0` and `X1` instances are the original PMOS and NMOS devices with additional layout-calculated source/drain diffusion areas (`ad`, `as`) and perimeters (`pd`, `ps`).
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- The `C0–C5` elements are **extracted parasitic capacitances** between the nodes in the layout.
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- The `R0` entry is a **resistive parasitic**, representing resistance in the interconnect or diffusion.
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These parasitics are important for accurate simulation of timing and analog performance, especially in high-speed or precision circuits.
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## Integration in Xschem/Ngspice (post-layout simulation)
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To simulate the extracted device, several approaches exist. In this example, we’ll keep the entire flow inside Xschem, using Ngspice as the simulator.
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Before continuing, please watch the following video by Stefan Schippers (creator of Xschem):
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https://www.youtube.com/watch?v=zs6JPXk074c&t=495s
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### Improved Shell Script
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As seen in the video, it’s possible to insert a netlist directly into a schematic using a symbol. Imagine a case where you’ve already generated a symbol for a design to use in a testbench — now, you can use that *same* symbol to simulate the extracted version with parasitics included.
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To enable this, a shell script has been created:
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`IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/run_kpex.sh`
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Relevant parts of this script are shown below.
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**Snippet 1** – User configuration:
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```
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###############################################################################
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# ⬇⬇⬇ USER CONFIGURATION ⬇⬇⬇ #
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###############################################################################
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# Activate Python environment (adjust this path to your Python venv activate script) Or if you python version is >3.12 ignore asuming klayout_pex is installed
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PYTHON_ENV="$HOME/misc/klayout_pex/bin/activate"
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# Example: /home/username/misc/klayout_pex/bin/activate
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# Path to Magic executable used by kpex (adjust if installed elsewhere)
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KPEX_MAGIC_EXE="$HOME/.local/bin/magic"
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# Example: /usr/local/bin/magic or ~/.local/bin/magic
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#Path to symbol
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SYM_DIR="../xschem_pre_layout/schematic/DIFF_COMPARATOR.sym" # Asuming you have a symbol for the DUT
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LAYOUT_DIR="../layout/DIFF_COMPARATOR.gds" # Path to the GDS file
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# Important: Path to your PDK root directory must be set externally in env variable PDK_ROOT, otherwise give absolute path
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PDK_NAME="ihp_sg13g2" # Your PDK name (must match PDK_ROOT contents)
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MAGICRC="$PDK_ROOT/$PDK/libs.tech/magic/ihp-sg13g2.magicrc" # The magicrc file for your PDK, used during extraction
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SCHEMATIC="../layout/lvs_netlist/DIFF_COMPARATOR.spice" # Spicefile of the comparator from Schematic or LVS (Used for pex to perform LVS and script to organize IO)
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```
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As seen above, a new variable has been added for the symbol. In this case, it points to the symbol used earlier for the comparator (from part_1) now copied to this directory. After that, the script runs `kpex`, just like we did for the inverter.
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The new logic comes in the next step.
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**Snippet 2** – Matching pin order and generating the new symbol:
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```
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# Find the generated spice file (assuming only one)
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spice_location=$(find ./pex_output -type f -name "*.spice" ! -name "*_dummy_schematic.spice" | head -n 1)
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if [[ -z "$spice_location" ]]; then
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echo "[ERROR] No .spice file found in pex_output directory"
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exit 1
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fi
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echo "[INFO] Found extracted spice file: $spice_location"
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# Run Python script to fix port ordering in the extracted netlist
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echo "[INFO] Reordering subcircuit pins to match original schematic..."
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echo "$spice_location"
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echo "$SCHEMATIC"
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python3 python/match_subckt_order.py "$spice_location" "$SCHEMATIC"
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echo "[INFO] Creating DUT symbol with pex netlist"
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python3 python/insert_netlist_to_sym.py "$spice_location" "$SYM_DIR" xschem_pex_symbol
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```
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After running `kpex`, the script looks for the generated PEX netlist and stores the path in the variable `spice_location`. It then calls a Python script `match_subckt_order.py` to fix the pin ordering.
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This step is important: the `.subckt` line in the netlist determines the pin order used for simulation, and when its generated in xschem the pin order will be the same for the symbol (which we will use for simulation). If the pin order of the PEX netlist doesn’t match the original netlist from xschem (also used for the symbol), simulation will give false results!
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Let’s look at an example:
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Original schematic netlist (used in LVS):
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for the inverter netlist, this is what it looks like when extracted (Top level is a subcircuit i.e LVS netlist in xschem)
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```
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.SUBCKT inverter Vdd Vin Vout Gnd
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*.PININFO Vout:B Vdd:B Vin:B Gnd:B
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M1 Gnd Vin Vout net2 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
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M2 Vout Vin Vdd net1 sg13_lv_pmos w=2.0u l=0.45u ng=1 m=1
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R1 Vdd net1 ntap1 A=6.084e-13 P=3.12e-06
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R2 Gnd net2 ptap1 A=6.084e-13 P=3.12e-06
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.ENDS
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```
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the direct output from PEX will give:
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```
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* NGSPICE file created from inverter.ext - technology: ihp-sg13g2
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.subckt inverter Vout Vin Gnd Vdd
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X0 Vout Vin Vdd Vdd sg13_lv_pmos ad=0.68p pd=4.68u as=0.68p ps=4.68u w=2u l=0.45u
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X1 Vout Vin Gnd Gnd sg13_lv_nmos ad=0.34p pd=2.68u as=0.34p ps=2.68u w=1u l=0.45u
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C0 Vout Vdd 0.13155f
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C1 Vout Vin 0.10077f
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C2 Vin Vdd 0.14482f
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R0 Vin Vin.n0 7.52248
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C3 Vout Gnd 0.39245f
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C4 Vin Gnd 0.64666f
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C5 Vdd Gnd 0.15308f
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.ends
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```
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Notice the difference in the `.subckt` pin order? That’s why we use the matching script.
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The script is located at:
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`IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/match_subckt_order.py`
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Finally, a second script is called to generate a new symbol containing the reordered PEX netlist:
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`IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_5_layout/comparator/pex/python/insert_netlist_to_sym.py`
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This creates a symbol placed in:
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`xschem_pex_symbol/`
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You can now use this symbol directly in your testbench to simulate the impact of parasitics.
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## Usage in Part_5
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In part_5, you’ll find a folder called `comparator`. Key folders inside are:
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- `layout/`: contains the comparator layout
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- `pex/`: contains the `run_pex.sh` script, Python helpers, and extraction output
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- `pex_output/`: holds the PEX netlist after extraction
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- `xschem_pex_symbol/`: contains the generated symbol with the PEX netlist
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- `xschem_post_layout/`: a copy of the part_1 testbenches, but updated to use the PEX symbol
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## Youtube Video
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To see this flow in action, please refer to the accompanying video:
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