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upload input pair layout

This commit is contained in:
PhillipRambo 2025-01-07 09:35:51 +01:00
parent 3abd3c5a9c
commit 2031391a13
14 changed files with 2240 additions and 2063 deletions
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1
.gitignore vendored
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@ -4,3 +4,4 @@
*.raw *.raw
*.spice *.spice
*.osdi *.osdi
*.cdl

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modules/module_1_bandgap_reference/part_1_OTA/layout/FMD_QNC_ROTest24_2.gds
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modules/module_1_bandgap_reference/part_1_OTA/layout/ota_simple_draft_1.gds
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34
modules/module_1_bandgap_reference/part_1_OTA/schematic/ota_testbench.sch
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@ -13,7 +13,7 @@ ypos2=2
divy=5 divy=5
subdivy=4 subdivy=4
unity=1 unity=1
x1=0 x1=-1.75
divx=5 divx=5
subdivx=8 subdivx=8
@ -35,20 +35,20 @@ autoload=0
sim_type=ac sim_type=ac
y2=180 y2=33.964
y1=-180 y1=-136.006
color=4 color=4
node=ph(vout) node=ph(vout)
x2=7} x2=5.25}
B 2 680 -1295 1480 -895 {flags=graph B 2 680 -1295 1480 -895 {flags=graph
y1=0.063 y1=33
y2=77 y2=74
ypos1=0 ypos1=0
ypos2=2 ypos2=2
divy=5 divy=5
subdivy=1 subdivy=1
unity=1 unity=1
x1=0 x1=-1.75
divx=5 divx=5
subdivx=8 subdivx=8
@ -60,16 +60,16 @@ dataset=-1
unitx=1 unitx=1
logx=1 logx=1
logy=0 logy=0
x2=7} x2=5.25}
B 2 1535 -1295 2335 -895 {flags=graph B 2 1535 -1295 2335 -895 {flags=graph
y1=52 y1=37
y2=67 y2=86
ypos1=0 ypos1=0
ypos2=2 ypos2=2
divy=5 divy=5
subdivy=1 subdivy=1
unity=1 unity=1
x1=0 x1=-1.75
divx=5 divx=5
subdivx=8 subdivx=8
@ -81,18 +81,18 @@ dataset=-1
unitx=1 unitx=1
logx=1 logx=1
logy=0 logy=0
x2=7 x2=5.25
color=4 color=4
node=cmrr} node=cmrr}
B 2 1525 -875 2325 -475 {flags=graph B 2 1525 -875 2325 -475 {flags=graph
y1=0.08 y1=0.05
y2=30 y2=28
ypos1=0 ypos1=0
ypos2=2 ypos2=2
divy=5 divy=5
subdivy=1 subdivy=1
unity=1 unity=1
x1=0 x1=-1.75
divx=5 divx=5
subdivx=8 subdivx=8
@ -104,7 +104,7 @@ dataset=-1
unitx=1 unitx=1
logx=1 logx=1
logy=0 logy=0
x2=7 x2=5.25
color=4 color=4
node=psrr} node=psrr}
N 775 -265 775 -235 { N 775 -265 775 -235 {
@ -273,7 +273,7 @@ value=4G
footprint=1206 footprint=1206
device="ceramic capacitor"} device="ceramic capacitor"}
C {gnd.sym} 210 -40 0 0 {name=l7 lab=GND} C {gnd.sym} 210 -40 0 0 {name=l7 lab=GND}
C {launcher.sym} 430 -635 0 0 {name=h5 C {launcher.sym} 420 -635 0 0 {name=h5
descr="load waves" descr="load waves"
tclcommand="xschem raw_read $netlist_dir/output_file.raw ac" tclcommand="xschem raw_read $netlist_dir/output_file.raw ac"
} }

6
modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/ota_testbench.spice
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@ -63,8 +63,8 @@ write output_file.raw
*.iopin vout *.iopin vout
XM4 net3 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1 XM4 net3 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
XM3 net1 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1 XM3 net1 net1 vss vss sg13_lv_nmos w=720n l=9.75u ng=1 m=1
XM1 net1 v- net2 vdd sg13_lv_pmos w=3.705u l=3.64u ng=1 m=1 XM1 net1 v- net2 vdd sg13_lv_pmos w=27.84u l=3.25u ng=4 m=1
XM2 net3 v+ net2 vdd sg13_lv_pmos w=3.705u l=3.64u ng=1 m=1 XM2 net3 v+ net2 vdd sg13_lv_pmos w=27.84u l=3.25u ng=4 m=1
XM5 net2 iout vdd vdd sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1 XM5 net2 iout vdd vdd sg13_lv_pmos w=5.3u l=1.95u ng=1 m=1
XM7 vout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1 XM7 vout iout vdd vdd sg13_lv_pmos w=75u l=2.08u ng=8 m=1
XM6 vout net3 vss vss sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1 XM6 vout net3 vss vss sg13_lv_nmos w=28.8u l=9.75u ng=4 m=1
@ -92,7 +92,7 @@ N1 out in1 in2 diff_amp_model
* following line specifies the location for the .osdi file so ngspice can use it. * following line specifies the location for the .osdi file so ngspice can use it.
pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp2.osdi pre_osdi /home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/diff_amp.osdi
.endc .endc

3683
modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/output_file.raw
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modules/module_1_bandgap_reference/part_1_OTA/schematic/simulations/tb_OTA_op.raw
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162
modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sch
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@ -5,91 +5,91 @@ K {}
V {} V {}
S {} S {}
E {} E {}
N 440 -280 440 -240 { N 450 -435 450 -395 {
lab=#net1} lab=#net1}
N 440 -280 550 -280 { N 450 -435 560 -435 {
lab=#net1} lab=#net1}
N 440 -150 650 -150 { N 660 -305 860 -305 {
lab=vss} lab=vss}
N 440 -210 440 -150 { N 560 -365 620 -365 {
lab=vss}
N 550 -210 610 -210 {
lab=#net1} lab=#net1}
N 550 -280 550 -210 { N 560 -435 560 -365 {
lab=#net1} lab=#net1}
N 480 -210 550 -210 { N 490 -365 560 -365 {
lab=#net1} lab=#net1}
N 650 -210 650 -150 { N 450 -495 450 -435 {
lab=vss}
N 440 -340 440 -280 {
lab=#net1} lab=#net1}
N 440 -370 650 -370 { N 450 -525 660 -525 {
lab=vdd} lab=vdd}
N 440 -420 440 -400 { N 450 -575 450 -555 {
lab=#net2} lab=#net2}
N 650 -420 650 -400 { N 660 -575 660 -555 {
lab=#net2} lab=#net2}
N 550 -420 650 -420 { N 560 -575 660 -575 {
lab=#net2} lab=#net2}
N 370 -370 400 -370 { N 380 -525 410 -525 {
lab=v-} lab=v-}
N 690 -370 720 -370 { N 700 -525 730 -525 {
lab=v+} lab=v+}
N 380 -470 510 -470 { N 390 -625 520 -625 {
lab=iout} lab=iout}
N 160 -420 160 -400 { N 170 -575 170 -555 {
lab=iout} lab=iout}
N 160 -420 210 -420 { N 170 -575 220 -575 {
lab=iout} lab=iout}
N 210 -470 230 -470 { N 220 -625 240 -625 {
lab=iout} lab=iout}
N 160 -520 160 -470 { N 170 -595 170 -575 {
lab=vdd}
N 160 -440 160 -420 {
lab=iout} lab=iout}
N 210 -470 210 -420 { N 220 -625 220 -575 {
lab=iout} lab=iout}
N 200 -470 210 -470 { N 210 -625 220 -625 {
lab=iout} lab=iout}
N 790 -470 810 -470 { N 800 -625 820 -625 {
lab=iout} lab=iout}
N 850 -520 850 -470 { N 860 -525 900 -525 {
lab=vdd}
N 850 -370 890 -370 {
lab=vout} lab=vout}
N 850 -440 850 -370 { N 860 -595 860 -525 {
lab=vout} lab=vout}
N 650 -245 650 -240 { N 660 -400 660 -395 {
lab=#net3} lab=#net3}
N 650 -150 850 -150 { N 560 -675 860 -675 {
lab=vss}
N 550 -520 850 -520 {
lab=vdd} lab=vdd}
N 160 -520 550 -520 { N 560 -595 560 -575 {
lab=vdd}
N 550 -520 550 -470 {
lab=vdd}
N 550 -440 550 -420 {
lab=#net2} lab=#net2}
N 440 -420 550 -420 { N 450 -575 560 -575 {
lab=#net2} lab=#net2}
N 850 -245 850 -150 { N 760 -400 820 -400 {
lab=#net3}
N 660 -495 660 -400 {
lab=#net3}
N 760 -460 760 -400 {
lab=#net3}
N 660 -400 760 -400 {
lab=#net3}
N 860 -460 860 -430 {
lab=vout}
N 820 -460 860 -460 {
lab=vout}
N 860 -525 860 -460 {
lab=vout}
N 450 -305 660 -305 {
lab=vss} lab=vss}
N 750 -245 810 -245 { N 860 -675 860 -625 {
lab=#net3} lab=vdd}
N 650 -340 650 -245 { N 170 -675 170 -625 {
lab=#net3} lab=vdd}
N 750 -305 750 -245 { N 560 -675 560 -625 {
lab=#net3} lab=vdd}
N 650 -245 750 -245 { N 170 -675 560 -675 {
lab=#net3} lab=vdd}
N 850 -305 850 -275 { N 450 -365 450 -305 {
lab=vout} lab=vss}
N 810 -305 850 -305 { N 860 -400 860 -305 {
lab=vout} lab=vss}
N 850 -370 850 -305 { N 660 -365 660 -305 {
lab=vout} lab=vss}
C {sg13g2_pr/sg13_lv_nmos.sym} 630 -210 2 1 {name=M4 C {sg13g2_pr/sg13_lv_nmos.sym} 640 -365 2 1 {name=M4
l=9.75u l=9.75u
w=720n w=720n
ng=1 ng=1
@ -97,7 +97,7 @@ m=1
model=sg13_lv_nmos model=sg13_lv_nmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/sg13_lv_nmos.sym} 460 -210 2 0 {name=M3 C {sg13g2_pr/sg13_lv_nmos.sym} 470 -365 2 0 {name=M3
l=9.75u l=9.75u
w=720n w=720n
ng=1 ng=1
@ -105,23 +105,23 @@ m=1
model=sg13_lv_nmos model=sg13_lv_nmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/sg13_lv_pmos.sym} 420 -370 0 0 {name=M1 C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1
l=3.64u l=3.7u
w=3.705u w=3.64u
ng=1 ng=1
m=1 m=2
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/sg13_lv_pmos.sym} 670 -370 0 1 {name=M2 C {sg13g2_pr/sg13_lv_pmos.sym} 680 -525 0 1 {name=M2
l=3.64u l=3.7u
w=3.705u w=3.64u
ng=1 ng=1
m=1 m=2
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/sg13_lv_pmos.sym} 530 -470 0 0 {name=M5 C {sg13g2_pr/sg13_lv_pmos.sym} 540 -625 0 0 {name=M5
l=1.95u l=1.95u
w=5.3u w=5.3u
ng=1 ng=1
@ -129,7 +129,7 @@ m=1
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/sg13_lv_pmos.sym} 830 -470 0 0 {name=M7 C {sg13g2_pr/sg13_lv_pmos.sym} 840 -625 0 0 {name=M7
l=2.08u l=2.08u
w=75u w=75u
ng=8 ng=8
@ -137,7 +137,7 @@ m=1
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/sg13_lv_nmos.sym} 830 -245 2 1 {name=M6 C {sg13g2_pr/sg13_lv_nmos.sym} 840 -400 2 1 {name=M6
l=9.75u l=9.75u
w=28.8u w=28.8u
ng=4 ng=4
@ -145,16 +145,15 @@ m=1
model=sg13_lv_nmos model=sg13_lv_nmos
spiceprefix=X spiceprefix=X
} }
C {iopin.sym} 370 -370 0 1 {name=p10 lab=v-} C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-}
C {iopin.sym} 720 -370 0 0 {name=p11 lab=v+} C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+}
C {iopin.sym} 550 -150 1 1 {name=p5 lab=vss} C {iopin.sym} 560 -305 1 1 {name=p5 lab=vss}
C {iopin.sym} 550 -520 1 1 {name=p1 lab=vdd} C {iopin.sym} 560 -675 1 1 {name=p1 lab=vdd}
C {iopin.sym} 160 -400 0 1 {name=p3 lab=iout} C {iopin.sym} 170 -555 0 1 {name=p3 lab=iout}
C {iopin.sym} 890 -370 0 0 {name=p8 lab=vout} C {iopin.sym} 900 -525 0 0 {name=p8 lab=vout}
C {lab_pin.sym} 230 -470 0 1 {name=p7 sig_type=std_logic lab=iout} C {lab_pin.sym} 240 -625 0 1 {name=p7 sig_type=std_logic lab=iout}
C {lab_pin.sym} 790 -470 0 0 {name=p6 sig_type=std_logic lab=iout} C {lab_pin.sym} 800 -625 0 0 {name=p6 sig_type=std_logic lab=iout}
C {lab_pin.sym} 550 -370 3 0 {name=p2 sig_type=std_logic lab=vdd} C {sg13g2_pr/sg13_lv_pmos.sym} 190 -625 0 1 {name=M9
C {sg13g2_pr/sg13_lv_pmos.sym} 180 -470 0 1 {name=M9
l=2.08u l=2.08u
w=75u w=75u
ng=8 ng=8
@ -162,10 +161,11 @@ m=1
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {sg13g2_pr/cap_cmim.sym} 780 -305 3 0 {name=C2 C {sg13g2_pr/cap_cmim.sym} 790 -460 3 0 {name=C2
model=cap_cmim model=cap_cmim
w=22.295e-6 w=22.295e-6
l=22.295e-6 l=22.295e-6
m=1 m=1
spiceprefix=X} spiceprefix=X}
C {lab_pin.sym} 380 -470 0 0 {name=p4 sig_type=std_logic lab=iout} C {lab_pin.sym} 390 -625 0 0 {name=p4 sig_type=std_logic lab=iout}
C {lab_pin.sym} 555 -525 3 0 {name=p2 sig_type=std_logic lab=vdd}

4
modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_MC.sch
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@ -167,12 +167,12 @@ C {devices/code_shown.sym} 20 -403.828125 0 0 {name=NGSPICE only_toplevel=false
value=" value="
.control .control
let run = 1 let run = 1
let mc_runs = 100 let mc_runs = 200
set curplot = new set curplot = new
set scratch = $curplot set scratch = $curplot
dowhile run <= mc_runs dowhile run <= mc_runs
reset reset
dc temp -50 100 5 dc temp 100 -50 -5
set run = $&run set run = $&run
set dc = $curplot set dc = $curplot
setplot $scratch setplot $scratch

4
modules/module_1_bandgap_reference/part_2_full_bgr/schematic/bandgap_reference.sch
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@ -212,7 +212,7 @@ C {devices/code_shown.sym} -440 -333.828125 0 0 {name=bandgap only_toplevel=true
.save all .save all
alter V1 dc 1.2 alter V1 dc 1.2
op op
dc TEMP -50 100 5 dc TEMP 100 -50 -5
write bgr_temp.raw write bgr_temp.raw
.endc .endc
@ -356,7 +356,7 @@ spiceprefix=X
b=0 b=0
m=1 m=1
} }
C {launcher.sym} 1171.40625 -793.28125 0 0 {name=h5 C {launcher.sym} 1171.40625 -813.28125 0 0 {name=h5
descr="load DC" descr="load DC"
tclcommand="xschem raw_read $netlist_dir/bgr_temp.raw dc" tclcommand="xschem raw_read $netlist_dir/bgr_temp.raw dc"
} }

BIN
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid.gds
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39
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/input_common_centroid_extracted.cir
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@ -1,28 +1,15 @@
* Extracted by KLayout with SG13G2 LVS runset on : 16/12/2024 11:10 * Extracted by KLayout with SG13G2 LVS runset on : 07/01/2025 08:25
.SUBCKT input_common_centroid .SUBCKT input_common_centroid v\x2d vdd v+ dn4 dn3
M$1 \$2 \$31 \$3 \$37 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p M$1 vdd vdd \$7 \$3 sg13_lv_pmos L=3.7u W=14.56u AS=4.9504p AD=4.9504p
+ PS=7.96u PD=7.96u + PS=31.84u PD=31.84u
M$2 \$3 \$32 \$4 \$37 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p M$2 \$7 v+ dn4 \$3 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PS=7.96u PD=7.96u + PD=15.92u
M$3 \$4 \$34 \$5 \$37 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p M$3 dn4 vdd vdd \$3 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PS=7.96u PD=7.96u + PD=15.92u
M$4 \$6 \$36 \$7 \$33 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p M$5 \$7 v\x2d dn3 \$3 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p
+ PS=7.96u PD=7.96u + PS=15.92u PD=15.92u
M$5 \$7 \$35 \$8 \$33 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p M$6 dn3 vdd vdd \$3 sg13_lv_pmos L=3.7u W=7.28u AS=2.4752p AD=2.4752p PS=15.92u
+ PS=7.96u PD=7.96u + PD=15.92u
M$6 \$8 \$30 \$9 \$33 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p R$13 \$3 vdd ntap1 A=169.1692p P=241.12u
+ PS=7.96u PD=7.96u
M$7 \$22 \$50 \$23 \$53 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
M$8 \$23 \$51 \$24 \$53 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
M$9 \$24 \$52 \$25 \$53 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
M$10 \$26 \$54 \$27 \$56 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
M$11 \$27 \$55 \$28 \$56 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
M$12 \$28 \$57 \$29 \$56 sg13_lv_pmos L=3.7u W=3.64u AS=1.2376p AD=1.2376p
+ PS=7.96u PD=7.96u
.ENDS input_common_centroid .ENDS input_common_centroid

83
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid.sch
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@ -7,8 +7,6 @@ S {}
E {} E {}
N 450 -495 450 -395 { N 450 -495 450 -395 {
lab=dn3} lab=dn3}
N 450 -525 660 -525 {
lab=well}
N 450 -575 450 -555 { N 450 -575 450 -555 {
lab=dn2} lab=dn2}
N 660 -575 660 -555 { N 660 -575 660 -555 {
@ -25,42 +23,44 @@ N 450 -575 560 -575 {
lab=dn2} lab=dn2}
N 660 -495 660 -400 { N 660 -495 660 -400 {
lab=dn4} lab=dn4}
N 230 -285 285 -285 { N 230 -315 230 -285 {
lab=well}
N 190 -315 190 -285 {
lab=vdd} lab=vdd}
N 230 -255 230 -235 { N 270 -255 270 -235 {
lab=dn4} lab=dn4}
N 75 -285 130 -285 {
lab=well}
N 35 -315 35 -285 { N 35 -315 35 -285 {
lab=vdd} lab=vdd}
N 75 -255 75 -235 { N 75 -255 75 -235 {
lab=dn3} lab=dn3}
N 190 -315 230 -315 { N 230 -315 270 -315 {
lab=vdd} lab=vdd}
N 35 -315 75 -315 { N 35 -315 75 -315 {
lab=vdd} lab=vdd}
N 560 -445 560 -415 { N 230 -425 230 -395 {
lab=well}
N 560 -355 560 -315 {
lab=#net1}
N 230 -395 285 -395 {
lab=well}
N 190 -425 190 -395 {
lab=vdd} lab=vdd}
N 230 -365 230 -345 { N 270 -365 270 -345 {
lab=dn2} lab=dn2}
N 75 -395 130 -395 {
lab=well}
N 35 -425 35 -395 { N 35 -425 35 -395 {
lab=vdd} lab=vdd}
N 75 -365 75 -345 { N 75 -365 75 -345 {
lab=dn2} lab=dn2}
N 190 -425 230 -425 { N 230 -425 270 -425 {
lab=vdd} lab=vdd}
N 35 -425 75 -425 { N 35 -425 75 -425 {
lab=vdd} lab=vdd}
N 560 -245 560 -205 {
lab=vdd}
N 75 -285 180 -285 {
lab=bulk}
N 75 -395 180 -395 {
lab=bulk}
N 450 -525 660 -525 {
lab=bulk}
N 270 -395 375 -395 {
lab=bulk}
N 270 -285 375 -285 {
lab=bulk}
N 560 -325 560 -300 {
lab=bulk}
C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1 C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1
l=3.7u l=3.7u
w=3.64u w=3.64u
@ -79,10 +79,8 @@ spiceprefix=X
} }
C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-} C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-}
C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+} C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+}
C {iopin.sym} 560 -315 2 1 {name=p1 lab=vdd} C {iopin.sym} 675 -205 2 1 {name=p1 lab=vdd}
C {lab_pin.sym} 450 -455 0 0 {name=p9 sig_type=std_logic lab=dn3} C {sg13g2_pr/sg13_lv_pmos.sym} 250 -285 0 0 {name=M8
C {lab_pin.sym} 660 -455 0 0 {name=p12 sig_type=std_logic lab=dn4}
C {sg13g2_pr/sg13_lv_pmos.sym} 210 -285 0 0 {name=M8
l=3.7u l=3.7u
w=3.64u w=3.64u
ng=1 ng=1
@ -90,7 +88,7 @@ m=2
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {lab_pin.sym} 190 -315 0 0 {name=p15 sig_type=std_logic lab=vdd} C {lab_pin.sym} 230 -315 0 0 {name=p15 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 55 -285 0 0 {name=M10 C {sg13g2_pr/sg13_lv_pmos.sym} 55 -285 0 0 {name=M10
l=3.7u l=3.7u
w=3.64u w=3.64u
@ -100,20 +98,10 @@ model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {lab_pin.sym} 35 -315 0 0 {name=p17 sig_type=std_logic lab=vdd} C {lab_pin.sym} 35 -315 0 0 {name=p17 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 560 -445 0 0 {name=p30 sig_type=std_logic lab=well}
C {sg13g2_pr/ntap1.sym} 560 -385 2 0 {name=R3
model=ntap1
spiceprefix=X
R=262.847.0
Imax=0.3e-6
}
C {lab_pin.sym} 560 -525 3 0 {name=p2 sig_type=std_logic lab=well}
C {lab_pin.sym} 130 -285 0 1 {name=p32 sig_type=std_logic lab=well}
C {lab_pin.sym} 285 -285 0 1 {name=p33 sig_type=std_logic lab=well}
C {lab_pin.sym} 560 -585 0 1 {name=p40 sig_type=std_logic lab=dn2} C {lab_pin.sym} 560 -585 0 1 {name=p40 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 75 -235 0 0 {name=p43 sig_type=std_logic lab=dn3} C {lab_pin.sym} 75 -235 0 0 {name=p43 sig_type=std_logic lab=dn3}
C {lab_pin.sym} 230 -235 0 0 {name=p18 sig_type=std_logic lab=dn4} C {lab_pin.sym} 270 -235 0 0 {name=p18 sig_type=std_logic lab=dn4}
C {sg13g2_pr/sg13_lv_pmos.sym} 210 -395 0 0 {name=M15 C {sg13g2_pr/sg13_lv_pmos.sym} 250 -395 0 0 {name=M15
l=3.7u l=3.7u
w=3.64u w=3.64u
ng=1 ng=1
@ -121,7 +109,7 @@ m=2
model=sg13_lv_pmos model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {lab_pin.sym} 190 -425 0 0 {name=p49 sig_type=std_logic lab=vdd} C {lab_pin.sym} 230 -425 0 0 {name=p49 sig_type=std_logic lab=vdd}
C {sg13g2_pr/sg13_lv_pmos.sym} 55 -395 0 0 {name=M16 C {sg13g2_pr/sg13_lv_pmos.sym} 55 -395 0 0 {name=M16
l=3.7u l=3.7u
w=3.64u w=3.64u
@ -131,7 +119,20 @@ model=sg13_lv_pmos
spiceprefix=X spiceprefix=X
} }
C {lab_pin.sym} 35 -425 0 0 {name=p50 sig_type=std_logic lab=vdd} C {lab_pin.sym} 35 -425 0 0 {name=p50 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 130 -395 0 1 {name=p51 sig_type=std_logic lab=well}
C {lab_pin.sym} 285 -395 0 1 {name=p52 sig_type=std_logic lab=well}
C {lab_pin.sym} 75 -345 0 0 {name=p53 sig_type=std_logic lab=dn2} C {lab_pin.sym} 75 -345 0 0 {name=p53 sig_type=std_logic lab=dn2}
C {lab_pin.sym} 230 -345 0 0 {name=p54 sig_type=std_logic lab=dn2} C {lab_pin.sym} 270 -345 0 0 {name=p54 sig_type=std_logic lab=dn2}
C {sg13g2_pr/ntap1.sym} 560 -270 0 0 {name=R1
model=ntap1
spiceprefix=X
w=13e-6
l=34e-6
}
C {iopin.sym} 450 -395 2 1 {name=p3 lab=dn3}
C {iopin.sym} 660 -405 2 1 {name=p4 lab=dn4}
C {lab_pin.sym} 560 -205 0 0 {name=p13 sig_type=std_logic lab=vdd}
C {lab_pin.sym} 375 -395 0 1 {name=p2 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 180 -395 0 1 {name=p5 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 180 -285 0 1 {name=p6 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 375 -285 0 1 {name=p7 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 560 -325 0 1 {name=p8 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 560 -525 1 1 {name=p9 sig_type=std_logic lab=bulk}

283
modules/module_1_bandgap_reference/part_3_layout/OTA_layout/input_pair/schematic_mod/input_common_centroid_alternative.sch Normal file
View File

@ -0,0 +1,283 @@
v {xschem version=3.4.5 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N 450 -495 450 -395 {
lab=dn3}
N 450 -525 660 -525 {
lab=bulk}
N 450 -575 450 -555 {
lab=dn2}
N 660 -575 660 -555 {
lab=dn2}
N 560 -575 660 -575 {
lab=dn2}
N 380 -525 410 -525 {
lab=v-}
N 700 -525 730 -525 {
lab=v+}
N 560 -595 560 -575 {
lab=dn2}
N 450 -575 560 -575 {
lab=dn2}
N 660 -495 660 -400 {
lab=dn4}
N 660 -335 715 -335 {
lab=bulk}
N 620 -365 620 -335 {
lab=#net1}
N 660 -305 660 -285 {
lab=dn4}
N 425 -345 480 -345 {
lab=bulk}
N 385 -375 385 -345 {
lab=#net2}
N 425 -315 425 -295 {
lab=dn3}
N 620 -365 660 -365 {
lab=#net1}
N 385 -375 425 -375 {
lab=#net2}
N 420 -645 475 -645 {
lab=bulk}
N 380 -675 380 -645 {
lab=#net3}
N 420 -615 420 -595 {
lab=dn2}
N 655 -655 710 -655 {
lab=bulk}
N 615 -685 615 -655 {
lab=#net4}
N 655 -625 655 -605 {
lab=dn2}
N 380 -675 420 -675 {
lab=#net3}
N 615 -685 655 -685 {
lab=#net4}
N 120 -375 120 -340 {
lab=bulk}
N 120 -285 120 -245 {
lab=vdd}
N 1170 -365 1225 -365 {
lab=bulk}
N 1130 -395 1130 -365 {
lab=#net5}
N 1170 -335 1170 -315 {
lab=dn4}
N 885 -355 940 -355 {
lab=bulk}
N 845 -385 845 -355 {
lab=#net6}
N 885 -325 885 -305 {
lab=dn3}
N 1130 -395 1170 -395 {
lab=#net5}
N 845 -385 885 -385 {
lab=#net6}
N 1090 -655 1145 -655 {
lab=bulk}
N 1050 -685 1050 -655 {
lab=#net7}
N 1090 -625 1090 -605 {
lab=dn2}
N 925 -645 980 -645 {
lab=bulk}
N 885 -675 885 -645 {
lab=#net8}
N 925 -615 925 -595 {
lab=dn2}
N 1050 -685 1090 -685 {
lab=#net7}
N 885 -675 925 -675 {
lab=#net8}
N 890 -495 890 -395 {
lab=dn3}
N 890 -525 1100 -525 {
lab=bulk}
N 890 -575 890 -555 {
lab=dn2}
N 1100 -575 1100 -555 {
lab=dn2}
N 1000 -575 1100 -575 {
lab=dn2}
N 820 -525 850 -525 {
lab=v-}
N 1140 -525 1170 -525 {
lab=v+}
N 1000 -595 1000 -575 {
lab=dn2}
N 890 -575 1000 -575 {
lab=dn2}
N 1100 -495 1100 -400 {
lab=dn4}
C {sg13g2_pr/sg13_lv_pmos.sym} 430 -525 0 0 {name=M1
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 680 -525 0 1 {name=M2
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {iopin.sym} 380 -525 0 1 {name=p10 lab=v-
m=1}
C {iopin.sym} 730 -525 0 0 {name=p11 lab=v+
m=1}
C {iopin.sym} 120 -245 2 1 {name=p1 lab=vdd}
C {lab_pin.sym} 450 -455 0 0 {name=p9 sig_type=std_logic lab=dn3
m=1}
C {lab_pin.sym} 660 -455 0 0 {name=p12 sig_type=std_logic lab=dn4
m=1}
C {sg13g2_pr/sg13_lv_pmos.sym} 640 -335 0 0 {name=M8
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 405 -345 0 0 {name=M10
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 120 -375 0 0 {name=p30 sig_type=std_logic lab=bulk}
C {lab_pin.sym} 560 -525 3 0 {name=p2 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 480 -345 0 1 {name=p32 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 715 -335 0 1 {name=p33 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 560 -585 0 1 {name=p40 sig_type=std_logic lab=dn2
m=1}
C {lab_pin.sym} 425 -295 0 0 {name=p43 sig_type=std_logic lab=dn3
m=1}
C {lab_pin.sym} 660 -285 0 0 {name=p18 sig_type=std_logic lab=dn4
m=1}
C {sg13g2_pr/sg13_lv_pmos.sym} 400 -645 0 0 {name=M15
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 635 -655 0 0 {name=M16
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 710 -655 0 1 {name=p51 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 475 -645 0 1 {name=p52 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 655 -605 0 0 {name=p53 sig_type=std_logic lab=dn2
m=1}
C {lab_pin.sym} 420 -595 0 0 {name=p54 sig_type=std_logic lab=dn2
m=1}
C {sg13g2_pr/ntap1.sym} 120 -310 2 0 {name=R1
model=ntap1
spiceprefix=X
w=13e-6
l=34e-6
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1150 -365 0 0 {name=M3
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 865 -355 0 0 {name=M4
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 940 -355 0 1 {name=p5 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 1225 -365 0 1 {name=p6 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 885 -305 0 0 {name=p7 sig_type=std_logic lab=dn3
m=1}
C {lab_pin.sym} 1170 -315 0 0 {name=p8 sig_type=std_logic lab=dn4
m=1}
C {sg13g2_pr/sg13_lv_pmos.sym} 1070 -655 0 0 {name=M5
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 905 -645 0 0 {name=M6
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {lab_pin.sym} 980 -645 0 1 {name=p16 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 1145 -655 0 1 {name=p19 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 925 -595 0 0 {name=p20 sig_type=std_logic lab=dn2
m=1}
C {lab_pin.sym} 1090 -605 0 0 {name=p21 sig_type=std_logic lab=dn2
m=1}
C {sg13g2_pr/sg13_lv_pmos.sym} 870 -525 0 0 {name=M7
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {sg13g2_pr/sg13_lv_pmos.sym} 1120 -525 0 1 {name=M9
l=3.7u
w=3.64u
ng=1
m=1
model=sg13_lv_pmos
spiceprefix=X
}
C {iopin.sym} 820 -525 0 1 {name=p22 lab=v-
m=1}
C {iopin.sym} 1170 -525 0 0 {name=p23 lab=v+
m=1}
C {lab_pin.sym} 890 -455 0 0 {name=p24 sig_type=std_logic lab=dn3
m=1}
C {lab_pin.sym} 1100 -455 0 0 {name=p25 sig_type=std_logic lab=dn4
m=1}
C {lab_pin.sym} 1000 -525 3 0 {name=p26 sig_type=std_logic lab=bulk
m=1}
C {lab_pin.sym} 1000 -585 0 1 {name=p27 sig_type=std_logic lab=dn2
m=1}
C {iopin.sym} 385 -375 2 0 {name=p3 lab=vdd}
C {iopin.sym} 620 -360 2 0 {name=p4 lab=vdd}
C {iopin.sym} 845 -380 2 0 {name=p13 lab=vdd}
C {iopin.sym} 1130 -390 2 0 {name=p14 lab=vdd}
C {iopin.sym} 1050 -675 2 0 {name=p15 lab=vdd}
C {iopin.sym} 885 -665 2 0 {name=p17 lab=vdd}
C {iopin.sym} 615 -680 2 0 {name=p28 lab=vdd}
C {iopin.sym} 380 -675 2 0 {name=p29 lab=vdd}