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# Two-Stage OTA Implementation in Xschem
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# Selecting the BJT Operating Point
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The first step in the procedure is to create the schematic for the two-stage OTA used in the design. Begin by creating an Xschem file with the following command:
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The first step in designing the bandgap reference in the structure we are working with is to select the appropriate relationship between the transistors Q1 and Q2 to achieve a suitable n-factor, while considering layout constraints. A 1:8 ratio with n = 8 provides favorable conditions for creating a robust common centroid layout, which will be discussed in more detail later.
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For the current bias, we assume a value of:
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$$I_{D3}=25\mu A$$
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and for the resistor value:
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$$R_3 = 45k\Omega$$
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From here lets investigate the resulting change in Vbe as the temperature varies from -30°C to 100°C. For this we create a new schematic given as
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```
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touch two_stage_OTA.sch
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touch vbesim.sch
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```
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Step 2: Instantiating Transistors
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Next, instantiate six MOSFETs (three PMOS and two NMOS) using the IHP Open PDK. Refer to the foundation markdown file from Module 0 for guidance on adding these components. Arrange the transistors as illustrated below, configuring their parameters accordingly:
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<p align="center"> <img src="../../../media/module_1/OTA_images/first_stage_img.png" width="1000" height="900" /> </p>
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To locate the required labels, open the Components Manager and search for iopin.sym under xschem_library/devices.
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# Two Stage OTA implimentation in Xschem
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First step in our procedure is to create the schematic for the OTA we will use in our design. To do this create a xschem file by typing
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```
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touch two_stage_OTA.sch
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```
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### Step 2: Instantiating Transistors
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Next, instantiate six MOSFETs (three PMOS and two NMOS) from the IHP Open PDK. Refer to the foundations markdown file from Module 0 for guidance on adding these components. Arrange the transistors as shown in the image below and configure their parameters accordingly.
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<p align="center">
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<img src="../../../media/module_1/OTA_images/first_stage_img.png" width="1000" height="900" />
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</p>
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To locate the necessary labels, open the Components Manager and search for `iopin.sym` under `xschem_library/devices`.
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### Transistor Dimensions for the First Stage
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For clarity, here are the transistor dimensions for the initial stage:
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- **M12**: $W = 7.41 \mu m, \ L = 3.64 \mu$
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- **M34**: $W = 0.72 \mu m, \ L = 9.75 \mu m$
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- **M5**: $W = 5.3 \mu m, \ L = 1.95 \mu m$
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- **M9**: $W = 75 \mu m, \ L = 2.08 \mu m , ng = 8$
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**Note:** Multi-fingered transistors are used to achieve higher transistor width than the maximal single finger width of $W_{max} = 10\mu m$. For example for transistor M9 an ng of 8 is used in order to achieve a total width of $75\mu m$ giving a single width of $75\mu m/8 = 9.375\mu m$.
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### Step 3: Designing the Output Stage
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Proceed to draw the output stage, which includes a Miller compensation capacitor. Follow the configuration shown below:
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<p align="center"> <img src="../../../media/module_1/OTA_images/full_system_img.png" width="1000" height="600" /> </p>
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Dimensions for the output stage components are as follows:
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- **M6** : $W = 28.8 \mu m, \ L = 9.75 \mu m, \ \ ng=4$
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- **M79**: The same as M9
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- **C1**: $W = 22.295\mu m, \ 22.295\mu m$
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For the Miller capacitor, use a metal-insulator-metal (MIM) capacitor with the given dimensions and multiplier to achieve an approximate capacitance of $C_C\approx 750 fF$. Ensure that each transistor’s bulk is connected correctly.
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### Creating a Symbol for the OTA
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With the schematic for the two-stage OTA complete, the next step is to create a symbol that represents the OTA as a single component. This symbol will simplify using the OTA in higher-level designs.
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### Step 1: Open the Schematic in Symbol Creation Mode
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Open the completed schematic (`two_stage_OTA.sch`) in Xschem and enter symbol creation mode by selecting **Symbol > Make symbol from schematic** (shortcut: **a**). This will allow you to create a graphical representation of the OTA, complete with input, output, and power pins. Close the schematic view, then open the newly created symbol file, which will have a `.sym` extension.
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### Step 2: Define Pin Locations
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Identify the key pins for the OTA, which will include:
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- **v+** and **v-**: Differential input pins
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- **vout**: Output pin
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- **vdd**: Positive power supply
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- **vss**: Ground/lowest potential
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- **iout**: Bias current
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Its also possible to remove the bias current pin and replace with an actual on chip bias!
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### Step 3: Adding and Placing Pins on the Symbol
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In symbol mode, Xschem automatically creates a small rectangle that includes pins with default names based on your schematic. Give the symbol an appropriate name and you should see the following
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<p align="center"> <img src="../../../media/module_1/OTA_images/symbol_1.png" width="500" height="400" /> </p>
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### Step 4: Designing the Symbol Shape
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Now, using the **Draw** tools in Xschem, modify the default rectangle to create a more fitting shape for the OTA. For a simple yet effective design, you can adjust the symbol by pulling in the existing edges to form a triangle, which is a common and recognizable shape for operational amplifiers. This shape helps to distinguish the input, output, and power connections clearly.
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If you’re interested in learning to create more complex shapes, there are resources on YouTube and other platforms. However, if you already have experience drawing schematic symbols, this step should feel straightforward. Refer to the provided images as a guide for arranging the shape and positioning the pins for a clean, organized symbol.
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<p align="center"> <img src="../../../media/module_1/OTA_images/ota_sym.png" width="500" height="400" /> </p>
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(Note: If the grid size and snapping values are too big, you can adjust at view - -> Set snap value/set grid spacing )
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### Step 5: Finalizing Pin Labels and Saving the Symbol
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Once the symbol shape and labels are in place, save your custom symbol by going to **File > Save Symbol As**. Choose a descriptive name, such as `two_stage_OTA.sym`, to clearly identify it for later use. This saved symbol can now be used in higher-level schematics to represent the OTA circuit in a compact, easily recognizable form.
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### Creating a Testbench Schematic for Frequency Response Analysis
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### Step 1: Create the Testbench Schematic
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Create a new schematic for the testbench where you will conduct the frequency response analysis of the OTA. This schematic will be used to assemble the necessary components and connections for the simulation.
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Use the following command to create a new schematic file:
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```
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touch ota_testbench.sch
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```
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### Step 2: Insert the OTA Symbol
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In your newly created testbench schematic, insert the **two_stage_OTA.sym** symbol that you created earlier. This symbol represents the OTA that you will analyze.
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To insert the symbol:
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1. Open the **Components Manager** by clicking **Insert Symbol** .
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2. Navigate to `current dir` > `two_stage_OTA.sym` (if the symbol is in your current directory!).
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3. Place the symbol on the schematic.
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You should now have the OTA symbol in the center of your schematic, ready to be connected to the voltage sources and feedback network.
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### Step 3: Setting Up the Open-Loop Testbench
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To set up the first testbench for simulating the open-loop frequency response of the OTA:
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1. **Add Voltage Sources**:
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- Insert two voltage sources: one for the positive input (with frequency magnitude) and one for VDD.
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- These voltage sources will apply both the DC bias (common mode) and the AC signal to the OTA input.
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2. **Ground VSS**:
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- Ensure that VSS is grounded, as the circuit operates within a voltage range of 0-1.2V.
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3. **Locate the Sources**:
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- You can find the required ideal voltage sources in the Xschem library.
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4. **Add Current Sources and Load Capacitor**:
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- Import a current source (`isource.sym`) and a load capacitor (`capa.sym`) from the library.
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- Set the following values:
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- Output current source ($I_{out}$): $80 \mu A$ (its set large so we can apply current source externally in real life!)
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- Load capacitor ($C_{load}$): $500 fF$.
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5. **Verify the Setup**:
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- At this point, your schematic should resemble the provided image, ensuring all components are placed and connected correctly.
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<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_1.png" width="1000" height="700" /> </p>
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As you may see there is additional components in the picture. The reasoning behind this can be seen in the following sections
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#### **Series Feedback with Infinite Inductor**
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1. Place an **infinite inductor** (or a very large inductance value, such as 1H) between the **OTA output** and the **negative input** (**In-**).
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2. This creates the series feedback path necessary for simulating the open-loop configuration.
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#### **Parallel Feedback with Infinite Capacitor**
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1. Add an **infinite capacitor** (or a very large capacitance, such as 1F) in parallel with the inductor.
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2. This parallel path complements the series feedback, contributing to shaping the OTA's frequency response.
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This feedback network establishes the conditions for analyzing the OTA's open-loop gain while ensuring proper DC biasing in the circuit.
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### Step 4: Include Transistor Models and Configure Simulation Settings
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To ensure the simulation runs correctly, you must specify the correct transistor models and process corner. This includes models for the **MIM capacitor** and **LV MOSFETs**. Follow these steps to configure the models using a code block component in Xschem:
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---
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#### **1. Add a Code Block Component**
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- Locate the **code block** (`code_shown.sym`) component in the Xschem library.
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- Place the code block in the schematic near the testbench setup for clarity.
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---
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#### **2. Configure the Code Block**
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Set the properties of the code block as follows:
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- **Name**: `MODEL`
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- **Only Top-Level**: Set to `false`.
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- to include subcircuits
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- **Format**: Set to `"tcleval( @value )"`.
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- This tells Xschem to evaluate the code block's value dynamically using Tcl scripting.
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---
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#### **3. Define the Model Paths**
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In the **Value** field, insert the following code:
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```
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.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
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.lib cornerMOSlv.lib mos_tt
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```
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#### **4. Explanation of the Code**
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- `.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ`
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- **`$::SG13G2_MODELS`**: This variable refers to the path where the SG13G2 process models are stored.
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- **`cornerCAP.lib`**: This file contains the models for the MIM capacitor.
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- **`cap_typ`**: Specifies the typical process corner for capacitors.
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- `.lib cornerMOSlv.lib mos_tt`
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- **`cornerMOSlv.lib`**: This file contains the low-voltage MOSFET models.
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- **`mos_tt`**: Specifies the **Typical-Typical (TT)** process corner for the MOSFETs
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By including this code block, you ensure the simulation has access to the correct models and process corners. At this point, your code block should resemble the provided image.
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<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_3.png" width="450" height="300" /> </p>
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### Extra Information About process corners: Understanding Variations in Semiconductor Fabrication
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Process corners are sets of predefined conditions that account for variations in semiconductor manufacturing processes. These variations affect the electrical characteristics of devices (like MOSFETs and capacitors) and can impact circuit performance. Simulating across process corners ensures your design works reliably under real-world manufacturing tolerances.
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---
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#### **Key Factors in Process Corners**
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Process corners arise due to differences in:
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1. **Doping Concentration**: Variations in dopant levels during fabrication.
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2. **Oxide Thickness**: Minor differences in gate oxide thickness.
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3. **Lithography and Etching**: Variability in physical dimensions of the devices.
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4. **Material Properties**: Changes in mobility and resistance of materials.
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---
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#### **The Standard Process Corners**
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1. **TT (Typical-Typical)**
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- Represents the average case, with both NMOS and PMOS devices performing at nominal levels.
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- Used for designing baseline circuit performance.
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2. **FF (Fast-Fast)**
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- Represents devices with higher-than-expected speeds due to lower resistance and higher mobility.
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- Useful for analyzing fast operation and timing issues.
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3. **SS (Slow-Slow)**
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- Models slower devices due to higher resistance and lower mobility.
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- Ensures the circuit functions under the worst-case performance conditions.
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4. **FS (Fast-Slow)** / **SF (Slow-Fast)**
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- Models mismatch between NMOS and PMOS speeds.
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- Critical for analyzing differential pair mismatches and complementary logic issues.
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---
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### Step 5: Setting Up Code for Simulation
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To analyze the frequency response and DC operating point of the OTA, we will incorporate a simulation code block written in **Ngspice**. This code block will handle the operating point (DC) analysis and AC frequency response analysis.
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#### **Importing the Ngspice Code Block**
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1. Import a **Code Block Shown** from the Xschem library, as previously described.
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2. Rename the block to **NGSPICE** for clarity.
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3. Ensure that the **netlisting** mode is set to **Spice netlist**:
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- Go to **Options → Netlist format/Symbol mode**.
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- Select **Spice netlist** from the dropdown.
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This step is crucial because the netlist format defines how Xschem interprets the schematic for Ngspice.
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#### **Setting Up the Operating Point Analysis**
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The first part of the Ngspice code block defines the **Operating Point (OP) Analysis**. This calculates the DC biasing conditions for the circuit and saves the results in a file named `tb_OTA_op.raw`. These results allow us to verify transistor parameters and explore deeper hierarchy levels (e.g., symbol-to-schematic mapping).
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Insert the following code into the **NGSPICE** block:
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```
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name=NGSPICE only_toplevel=false
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value="
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.control
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op
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save all
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write tb_OTA_op.raw
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.endc
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```
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- **`op`**: Performs the DC operating point analysis.
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- **`save all`**: Saves all simulation data, including node voltages and branch currents.
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- **`write tb_OTA_op.raw`**: Outputs the operating point results to a raw file
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#### **Defining the AC Frequency Response Analysis**
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The second part of the code block sets up the **AC Analysis**, which computes the open-loop gain and phase response of the OTA. The AC simulation sweeps frequencies logarithmically (decades) from $1Hz$, $10MHz$ with 100 points per decade.
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Append the following code to the **NGSPICE** block:
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```
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.control
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op
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ac dec 100 1 10e6
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save all
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let Av = db(v(vout))
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let phase = 180*cph(vout)/pi
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write output_file.raw
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.endc
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```
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- **`ac dec 100 1 10e6`**: Defines an AC sweep with:
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- **`dec`**: Logarithmic frequency scaling.
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- **`100`**: 100 points per decade.
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- **`1` and `10e6`**: Frequency range from 1 Hz1 \, \text{Hz}1Hz to 10 MHz10 \, \text{MHz}10MHz.
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- **`let Av = db(v(vout))`**: Computes the open-loop gain $A_V$ in decibels.
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- **`let phase = 180*cph(vout)/pi`**: Converts the phase of the output voltage from radians to degrees.
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- **`write output_file.raw`**: Saves the AC analysis results to a raw file for further processing.
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#### **Verifying the Code Block**
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The complete code block should look as shown in the image below:
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<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_4.png" width="250" height="250" /> </p>
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### Step 6: Running simulation and confirming operation
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Now that all components are in place, you can run the simulation. This will allow you to analyze the **open-loop** of the OTA. For this navigate to netlist in the upper right corner to generate the netlist and after this press simulate. At this point a terminal should pop up showing something like this
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```
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Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
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Using SPARSE 1.3 as Direct Linear Solver
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Note: Starting dynamic gmin stepping
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Note: Dynamic gmin stepping completed
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No. of Data Rows : 1
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binary raw file "tb_OTA_op.raw"
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Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
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Using SPARSE 1.3 as Direct Linear Solver
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Note: Starting dynamic gmin stepping
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Note: Dynamic gmin stepping completed
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No. of Data Rows : 1
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Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
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Using SPARSE 1.3 as Direct Linear Solver
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Note: Starting dynamic gmin stepping
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Note: Dynamic gmin stepping completed
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Reference value : 1.00000e+00
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No. of Data Rows : 701
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binary raw file "output_file.raw"
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```
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At this point you can write plot Av or write plot phase to see the magnitude or the phase response of the amplifier. To better analyse the results in terms of gain and stability. We will create two plots where we can print the plots in. For this navigate to simulation tab -> graphs and select add vaeform graph. Create two of these. Place them in the testbench above eachother. From the same place also add waveform reload launcher. From here click the waveform reload launcher and specify you raw file, as follows:
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```
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name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/output_file.raw ac"
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```
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After this press ctrl and left click the arrow, and after this double click the bottom plot. From here you should see all the avaliable signals for plotting and select the ph(vout). This gives the phase response. This is used instead of the statement we defined since xschem automatically saves the data in the raw format as a complex number with a real and imaginary number. From check the Log X box and set the x max to 6.65 and the y min to -200 and Y max to 0. For the second plot double press this and now select the Av to be plotted. From here also check the log x box, set the x axis to the same as for the phase plot and the Y max to 77. From here you should see the same as in the following picture
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<p align="center"> <img src="../../../media/module_1/OTA_images/ac_resp.png" width="800" height="700" /> </p>
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Refer to the provided images and simulations to confirm the setup and ensure everything is correctly configured for the analysis.
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### Step 9: Insert a Second OTA Symbol for CMRR Analysis
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After confirming the open-loop, you will introduce a second **OTA symbol** to test the common mode rejection ratio
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1. Insert another **two_stage_OTA.sym** symbol into the schematic.
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2. Connect the two inputs together
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By now you should have the following setup
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<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_5.png" width="1000" height="500" /> </p>
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Now the code block should also have an extended definition where we will define our CMRR calculation as
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```
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let CMRR = db((v(vout)/v(vp))/(v(vout1)/v(vp)))
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```
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Now you can add another graph window, or just use the XTerm terminal. You should now see a CMRR in the same region as the following image
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<p align="center"> <img src="../../../media/module_1/OTA_images/CMRR.png" width="500" height="500" /> </p>
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### Step 9: Insert a Third OTA Symbol for PSRR Analysis
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For the power supply rejection ratio we don't expect to good results since we are using a topology where the impedance from the supply to the output really isn't that high. If you want to improve this you can change topology or implementing telescopic approach with cascode mirrors. The power supply rejection ratio is given as
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$$PSRR = 20 \cdot log\left(\frac{\Delta V_{out}}{\Delta V_{V_{DD(AC)}}}\right) $$
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For the simulation setup, we refer to the description below
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1. Insert another **two_stage_OTA.sym** symbol into the schematic.
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2. Use the same structure as for the open loop gain but set the positive input only to common mode DC and no AC signal!
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3. For the supply now add a AC signal of 1 and a phase of 0
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For the setup it should something like this
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<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_6.png" width="700" height="600" /> </p>
|
||||
|
||||
|
||||
For the code block you can define the PSRR as given
|
||||
|
||||
```
|
||||
let PSRR = db(v(vout2)/v(VDDac))
|
||||
|
||||
```
|
||||
For the power supply rejection ratio you should see something like this:
|
||||
<p align="center"> <img src="../../../media/module_1/OTA_images/PSRR.png" width="500" height="500" /> </p>
|
||||
|
||||
|
||||
In this schematic we want to instaciate the following
|
||||
|
||||
- res.sym -->> values = 45k
|
||||
- sg13g2_pr/pnpMPA.sym -->> $w = 5.0\mu m \ \ l = 5.0\mu m$
|
||||
- isource.sym -->> name=I0 value=25e-6
|
||||
- vsource.sym -->> name=V1 value=1.2 savecurrent=false
|
||||
|
|
|
|||
Loading…
Reference in New Issue