create xschemrc for all dirs
This commit is contained in:
PhillipRambo
parent
e73bcfe452
commit
156e0c90fa
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@ -1,5 +1,6 @@
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/misc/
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**/.vscode/
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**/sar_logic_obj_dir/
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**/.ipynb_checkpoints/
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*.raw
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*.spice
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@ -8,4 +9,7 @@
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*.dat
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*.txt
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*.npy
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*.so
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*.out
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*.vcd
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@ -0,0 +1,18 @@
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# xschemrc - Custom configuration file for xschem
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# This file sources another xschemrc file from a known location
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# Source the base configuration from a known location
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source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
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# (Optional) Add any custom overrides or extensions below
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# set xschem_library_path /home/user/my_libs
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# set xschem_gui_font "Monospace 10"
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#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
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###only if you dont have this setup already ###
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###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
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#### Add custom libraries (directories with .lib files)
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append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
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@ -1,5 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -311,7 +310,6 @@ C {lab_pin.sym} 335 65 0 0 {name=p8 sig_type=std_logic lab=VDDac}
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C {vsource.sym} 95 230 0 0 {name=V4 value="DC 0.6"
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}
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C {gnd.sym} 95 280 0 0 {name=l12 lab=GND}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_2_full_bgr/schematic/verilog/veriloga_tbs/diff_amp.sym} 1310 120 0 0 {name=U1 model=diff_amp_cell spiceprefix=X}
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C {ind.sym} 1275 330 1 0 {name=L16
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m=1
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value=4G
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@ -325,6 +323,7 @@ device="ceramic capacitor"}
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C {gnd.sym} 1180 400 0 0 {name=l17 lab=GND}
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C {iopin.sym} 1570 120 0 0 {name=p9 lab=vout3}
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C {lab_pin.sym} 1110 80 0 0 {name=p14 sig_type=std_logic lab=vp}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 350 240 0 0 {name=x4}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 360 -410 0 0 {name=x1}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 1305 -255 0 0 {name=x2}
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C {two_stage_OTA.sym} 360 -410 0 0 {name=x1}
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C {two_stage_OTA.sym} 350 240 0 0 {name=x2}
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C {two_stage_OTA.sym} 1305 -255 0 0 {name=x3}
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C {diff_amp.sym} 1310 120 0 0 {name=U1 model=diff_amp_cell spiceprefix=X}
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@ -1,5 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -95,4 +94,4 @@ C {launcher.sym} 430 -635 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/output_file.raw ac"
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}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} 310 -550 0 0 {name=x1}
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C {two_stage_OTA.sym} 310 -550 0 0 {name=x1}
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@ -0,0 +1,19 @@
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# xschemrc - Custom configuration file for xschem
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# This file sources another xschemrc file from a known location
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# Source the base configuration from a known location
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source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
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# (Optional) Add any custom overrides or extensions below
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# set xschem_library_path /home/user/my_libs
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# set xschem_gui_font "Monospace 10"
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#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
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###only if you dont have this setup already ###
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###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
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#### Add custom libraries (directories with .lib files)
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append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
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append XSCHEM_LIBRARY_PATH :../schematic/
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append XSCHEM_LIBRARY_PATH :../../part_2_full_bgr/schematic/verilog/veriloga_tbs/
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@ -1,5 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -228,7 +227,6 @@ model=sg13_lv_pmos
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spiceprefix=X
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}
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C {lab_pin.sym} -485 -980 0 1 {name=p5 sig_type=std_logic lab=vdd}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} -260 -695 0 0 {name=x2}
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C {lab_pin.sym} -275 -795 0 1 {name=p1 sig_type=std_logic lab=vdd}
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C {gnd.sym} -275 -520 0 1 {name=l4 lab=GND}
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C {isource.sym} -350 -565 0 1 {name=I1 value=80u}
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@ -326,3 +324,4 @@ w=18.195e-6
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l=18.195e-6
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m=1
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spiceprefix=X}
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C {two_stage_OTA.sym} -260 -695 0 0 {name=x1}
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@ -1,5 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -264,7 +263,6 @@ model=sg13_lv_pmos
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spiceprefix=X
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}
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C {lab_pin.sym} -485 -980 0 1 {name=p5 sig_type=std_logic lab=vdd}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} -260 -695 0 0 {name=x2}
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C {lab_pin.sym} -275 -795 0 1 {name=p1 sig_type=std_logic lab=vdd}
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C {gnd.sym} -275 -520 0 1 {name=l4 lab=GND}
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C {isource.sym} -350 -565 0 1 {name=I1 value=80u}
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@ -370,3 +368,4 @@ w=18.195e-6
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l=18.195e-6
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m=1
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spiceprefix=X}
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C {two_stage_OTA.sym} -260 -695 0 0 {name=x1}
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@ -1,5 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -235,7 +234,6 @@ model=sg13_lv_pmos
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spiceprefix=X
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}
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C {lab_pin.sym} -485 -980 0 1 {name=p5 sig_type=std_logic lab=vdd}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_1_bandgap_reference/part_1_OTA/schematic/two_stage_OTA.sym} -260 -695 0 0 {name=x2}
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C {lab_pin.sym} -275 -795 0 1 {name=p1 sig_type=std_logic lab=vdd}
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C {gnd.sym} -275 -520 0 1 {name=l4 lab=GND}
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C {isource.sym} -350 -565 0 1 {name=I1 value=80u}
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@ -331,3 +329,4 @@ C {launcher.sym} 1181.40625 -918.28125 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/bgr_temp.raw dc"
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}
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C {two_stage_OTA.sym} -260 -695 0 0 {name=x1}
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# xschemrc - Custom configuration file for xschem
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# This file sources another xschemrc file from a known location
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# Source the base configuration from a known location
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source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
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# (Optional) Add any custom overrides or extensions below
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# set xschem_library_path /home/user/my_libs
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# set xschem_gui_font "Monospace 10"
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#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
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###only if you dont have this setup already ###
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###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
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#### Add custom libraries (directories with .lib files)
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append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
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append XSCHEM_LIBRARY_PATH :../../part_1_OTA/schematic/
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -219,7 +218,6 @@ C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
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C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
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C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"}
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C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vinp}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
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C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vinp}
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C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
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@ -252,3 +250,4 @@ footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 460 -140 0 0 {name=l6 lab=GND}
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C {gnd.sym} 460 -300 2 0 {name=l7 lab=GND}
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C {dynamic_comparator.sym} 270 -220 0 0 {name=x1}
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@ -1,5 +1,4 @@
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v {xschem version=3.4.5 file_version=1.2
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}
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v {xschem version=3.4.6 file_version=1.2}
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G {}
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K {}
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V {}
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@ -71,7 +70,6 @@ C {lab_pin.sym} -420 -180 2 0 {name=p1 sig_type=std_logic lab=clk}
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C {gnd.sym} -570 -70 0 0 {name=l2 lab=GND}
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C {vsource.sym} -210 -130 0 0 {name=V2 value="PULSE(595e-3 605e-3 0 tr 1S 1S)"}
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C {lab_pin.sym} -210 -180 2 0 {name=p2 sig_type=std_logic lab=vinp}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 270 -220 0 0 {name=x1}
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C {lab_pin.sym} 60 -280 2 1 {name=p5 sig_type=std_logic lab=vinp}
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C {lab_pin.sym} 200 -350 2 0 {name=p6 sig_type=std_logic lab=vdd}
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C {lab_pin.sym} 60 -220 2 1 {name=p7 sig_type=std_logic lab=vbias}
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@ -136,3 +134,4 @@ value="
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.endc
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"}
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C {dynamic_comparator.sym} 270 -220 0 0 {name=x1}
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Before Width: | Height: | Size: 148 KiB After Width: | Height: | Size: 148 KiB |
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@ -0,0 +1,19 @@
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# xschemrc - Custom configuration file for xschem
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# This file sources another xschemrc file from a known location
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# Source the base configuration from a known location
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source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
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# (Optional) Add any custom overrides or extensions below
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# set xschem_library_path /home/user/my_libs
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# set xschem_gui_font "Monospace 10"
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#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
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###only if you dont have this setup already ###
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###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
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#### Add custom libraries (directories with .lib files)
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append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
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append XSCHEM_LIBRARY_PATH :../schematic/
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@ -0,0 +1 @@
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Transmission Gate
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@ -124,7 +124,6 @@ C {launcher.sym} 820 -310 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/T_gate_tb.raw tran"
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}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 240 -850 0 0 {name=x3}
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C {gnd.sym} 260 -690 0 0 {name=l5 lab=GND}
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C {gnd.sym} 260 -640 0 0 {name=l6 lab=GND}
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C {lab_pin.sym} 260 -730 0 0 {name=p6 sig_type=std_logic lab=vdd}
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@ -140,5 +139,6 @@ value=7p
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 570 -770 0 0 {name=l7 lab=GND}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 400 -1020 0 0 {name=x1}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 400 -690 0 0 {name=x2}
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C {inverter.sym} 240 -850 0 0 {name=x1}
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C {T_gate.sym} 400 -1020 0 0 {name=x2}
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C {T_gate.sym} 400 -690 0 0 {name=x3}
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@ -0,0 +1,20 @@
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# xschemrc - Custom configuration file for xschem
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# This file sources another xschemrc file from a known location
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# Source the base configuration from a known location
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source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
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# (Optional) Add any custom overrides or extensions below
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# set xschem_library_path /home/user/my_libs
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# set xschem_gui_font "Monospace 10"
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#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
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###only if you dont have this setup already ###
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###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
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#### Add custom libraries (directories with .lib files)
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append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
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append XSCHEM_LIBRARY_PATH :../../bootstrap_switch/schematic/
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append XSCHEM_LIBRARY_PATH :../schematic/
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@ -74,7 +74,6 @@ tran 100u 1.463m
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write test_bootstrap.raw
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.endc
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" }
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sym} 340 -430 0 0 {name=x1}
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C {vsource.sym} 60 -370 0 0 {name=V1 value="PULSE(0 5 0 1n 1n 0.5u 1u)"}
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C {gnd.sym} 60 -320 0 1 {name=l2 lab=GND}
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C {lab_pin.sym} 60 -430 0 0 {name=p1 sig_type=std_logic lab=clk}
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@ -99,3 +98,4 @@ value=7p
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footprint=1206
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device="ceramic capacitor"}
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C {gnd.sym} 500 -300 0 1 {name=l1 lab=GND}
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C {bootstrap_switch.sym} 340 -430 0 0 {name=x1}
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@ -0,0 +1,19 @@
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# xschemrc - Custom configuration file for xschem
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# This file sources another xschemrc file from a known location
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# Source the base configuration from a known location
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source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
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# (Optional) Add any custom overrides or extensions below
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# set xschem_library_path /home/user/my_libs
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# set xschem_gui_font "Monospace 10"
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#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
|
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###only if you dont have this setup already ###
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###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
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#### Add custom libraries (directories with .lib files)
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append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
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append XSCHEM_LIBRARY_PATH :../schematic/
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@ -107,7 +107,6 @@ tclcommand="xschem raw_read $netlist_dir/nand_tb.raw tran"
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C {devices/lab_pin.sym} 140 440 2 0 {name=p1 sig_type=std_logic lab=B}
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C {devices/gnd.sym} 140 530 0 0 {name=l1 lab=GND}
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C {devices/vsource.sym} 140 490 0 0 {name=V2 value="dc 0 ac 0 PULSE(0 1 0 1n 1n 1u 2u)"}
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C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/nand_gate/schematic/nand_gate.sym} 720 380 0 0 {name=x1}
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C {devices/lab_pin.sym} 550 340 2 1 {name=p2 sig_type=std_logic lab=A}
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C {devices/lab_pin.sym} 550 400 2 1 {name=p3 sig_type=std_logic lab=B}
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C {devices/lab_pin.sym} 660 260 2 1 {name=p4 sig_type=std_logic lab=vdd}
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@ -119,3 +118,4 @@ value=50f
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footprint=1206
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device="ceramic capacitor"}
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C {opin.sym} 820 370 0 0 {name=p5 lab=Vo}
|
||||
C {nand_gate.sym} 720 380 0 0 {name=x1}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
# xschemrc - Custom configuration file for xschem
|
||||
# This file sources another xschemrc file from a known location
|
||||
|
||||
# Source the base configuration from a known location
|
||||
source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
|
||||
|
||||
# (Optional) Add any custom overrides or extensions below
|
||||
# set xschem_library_path /home/user/my_libs
|
||||
# set xschem_gui_font "Monospace 10"
|
||||
|
||||
#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
|
||||
###only if you dont have this setup already ###
|
||||
###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
|
||||
|
||||
|
||||
#### Add custom libraries (directories with .lib files)
|
||||
append XSCHEM_LIBRARY_PATH :$PDK_ROOT/ihp-sg13g2/libs.tech/xschem
|
||||
append XSCHEM_LIBRARY_PATH :../schematic/
|
||||
|
||||
|
|
@ -28,7 +28,7 @@ N 300 -870 300 -860 {lab=gnd}
|
|||
N 580 -940 630 -940 {lab=S_MSB}
|
||||
N 1040 -700 1040 -670 {lab=D6}
|
||||
N 1120 -780 1180 -780 {lab=S6}
|
||||
N 1040 -1030 1040 -860 {lab=#net3}
|
||||
N 1040 -1030 1040 -860 {lab=#net2}
|
||||
N 1120 -1110 1180 -1110 {lab=S6}
|
||||
N 1180 -950 1180 -780 {lab=S6}
|
||||
N 1180 -1110 1180 -950 {lab=S6}
|
||||
|
|
@ -50,7 +50,7 @@ N 900 -880 900 -870 {lab=gnd}
|
|||
N 1180 -950 1230 -950 {lab=S6}
|
||||
N 1610 -710 1610 -680 {lab=D5}
|
||||
N 1690 -790 1750 -790 {lab=S5}
|
||||
N 1610 -1040 1610 -870 {lab=#net4}
|
||||
N 1610 -1040 1610 -870 {lab=#net3}
|
||||
N 1690 -1120 1750 -1120 {lab=S5}
|
||||
N 1750 -960 1750 -790 {lab=S5}
|
||||
N 1750 -1120 1750 -960 {lab=S5}
|
||||
|
|
@ -72,7 +72,7 @@ N 1470 -890 1470 -880 {lab=gnd}
|
|||
N 1750 -960 1800 -960 {lab=S5}
|
||||
N 440 -80 440 -50 {lab=D4}
|
||||
N 520 -160 580 -160 {lab=S4}
|
||||
N 440 -410 440 -240 {lab=#net5}
|
||||
N 440 -410 440 -240 {lab=#net4}
|
||||
N 520 -490 580 -490 {lab=S4}
|
||||
N 580 -330 580 -160 {lab=S4}
|
||||
N 580 -490 580 -330 {lab=S4}
|
||||
|
|
@ -94,7 +94,7 @@ N 300 -260 300 -250 {lab=gnd}
|
|||
N 580 -330 630 -330 {lab=S4}
|
||||
N 1040 -90 1040 -60 {lab=D3}
|
||||
N 1120 -170 1180 -170 {lab=S3}
|
||||
N 1040 -420 1040 -250 {lab=#net6}
|
||||
N 1040 -420 1040 -250 {lab=#net5}
|
||||
N 1120 -500 1180 -500 {lab=S3}
|
||||
N 1180 -340 1180 -170 {lab=S3}
|
||||
N 1180 -500 1180 -340 {lab=S3}
|
||||
|
|
@ -116,7 +116,7 @@ N 900 -270 900 -260 {lab=gnd}
|
|||
N 1180 -340 1230 -340 {lab=S3}
|
||||
N 1620 -100 1620 -70 {lab=D2}
|
||||
N 1700 -180 1760 -180 {lab=S2}
|
||||
N 1620 -430 1620 -260 {lab=#net7}
|
||||
N 1620 -430 1620 -260 {lab=#net6}
|
||||
N 1700 -510 1760 -510 {lab=S2}
|
||||
N 1760 -350 1760 -180 {lab=S2}
|
||||
N 1760 -510 1760 -350 {lab=S2}
|
||||
|
|
@ -138,7 +138,7 @@ N 1480 -280 1480 -270 {lab=gnd}
|
|||
N 1760 -350 1810 -350 {lab=S2}
|
||||
N 2190 -110 2190 -80 {lab=D1}
|
||||
N 2270 -190 2330 -190 {lab=S1}
|
||||
N 2190 -440 2190 -270 {lab=#net8}
|
||||
N 2190 -440 2190 -270 {lab=#net7}
|
||||
N 2270 -520 2330 -520 {lab=S1}
|
||||
N 2330 -360 2330 -190 {lab=S1}
|
||||
N 2330 -520 2330 -360 {lab=S1}
|
||||
|
|
@ -159,67 +159,46 @@ N 2050 -420 2050 -410 {lab=vdd}
|
|||
N 2050 -290 2050 -280 {lab=gnd}
|
||||
N 2330 -360 2380 -360 {lab=S1}
|
||||
C {iopin.sym} 630 -940 0 0 {name=p5 lab=S_MSB}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 280 -930 0 0 {name=x3}
|
||||
C {lab_pin.sym} 300 -810 0 0 {name=p6 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 300 -1140 0 0 {name=p7 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 300 -1100 0 0 {name=p8 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 300 -1000 0 0 {name=p4 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 440 -1100 0 0 {name=x1}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 440 -770 0 0 {name=x2}
|
||||
C {iopin.sym} 1230 -950 0 0 {name=p13 lab=S6}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 880 -940 0 0 {name=x7}
|
||||
C {lab_pin.sym} 900 -820 0 0 {name=p14 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 900 -1150 0 0 {name=p15 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 900 -1110 0 0 {name=p16 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 900 -1010 0 0 {name=p18 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1040 -1110 0 0 {name=x8}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1040 -780 0 0 {name=x9}
|
||||
C {iopin.sym} 190 -930 0 1 {name=p19 lab=D_MSB}
|
||||
C {iopin.sym} 790 -940 0 1 {name=p11 lab=D6}
|
||||
C {iopin.sym} 1800 -960 0 0 {name=p17 lab=S5}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 1450 -950 0 0 {name=x10}
|
||||
C {lab_pin.sym} 1470 -830 0 0 {name=p20 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 1470 -1160 0 0 {name=p21 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 1470 -1120 0 0 {name=p22 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 1470 -1020 0 0 {name=p23 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1610 -1120 0 0 {name=x11}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1610 -790 0 0 {name=x12}
|
||||
C {iopin.sym} 1360 -950 0 1 {name=p24 lab=D5}
|
||||
C {iopin.sym} 630 -330 0 0 {name=p25 lab=S4}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 280 -320 0 0 {name=x13}
|
||||
C {lab_pin.sym} 300 -200 0 0 {name=p26 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 300 -530 0 0 {name=p27 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 300 -490 0 0 {name=p28 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 300 -390 0 0 {name=p29 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 440 -490 0 0 {name=x14}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 440 -160 0 0 {name=x15}
|
||||
C {iopin.sym} 1230 -340 0 0 {name=p30 lab=S3}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 880 -330 0 0 {name=x16}
|
||||
C {lab_pin.sym} 900 -210 0 0 {name=p31 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 900 -540 0 0 {name=p32 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 900 -500 0 0 {name=p33 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 900 -400 0 0 {name=p34 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1040 -500 0 0 {name=x17}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1040 -170 0 0 {name=x18}
|
||||
C {iopin.sym} 1810 -350 0 0 {name=p35 lab=S2}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 1460 -340 0 0 {name=x19}
|
||||
C {lab_pin.sym} 1480 -220 0 0 {name=p36 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 1480 -550 0 0 {name=p37 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 1480 -510 0 0 {name=p38 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 1480 -410 0 0 {name=p39 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1620 -510 0 0 {name=x20}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 1620 -180 0 0 {name=x21}
|
||||
C {iopin.sym} 190 -320 0 1 {name=p40 lab=D4}
|
||||
C {iopin.sym} 790 -330 0 1 {name=p41 lab=D3}
|
||||
C {iopin.sym} 1370 -340 0 1 {name=p42 lab=D2}
|
||||
C {iopin.sym} 2380 -360 0 0 {name=p43 lab=S1}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/inverter.sym} 2030 -350 0 0 {name=x22}
|
||||
C {lab_pin.sym} 2050 -230 0 0 {name=p44 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 2050 -560 0 0 {name=p45 sig_type=std_logic lab=vdd}
|
||||
C {lab_pin.sym} 2050 -520 0 0 {name=p46 sig_type=std_logic lab=vref}
|
||||
C {lab_pin.sym} 2050 -420 0 0 {name=p47 sig_type=std_logic lab=vdd}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 2190 -520 0 0 {name=x23}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/T_gate/schematic/T_gate.sym} 2190 -190 0 0 {name=x24}
|
||||
C {iopin.sym} 1940 -350 0 1 {name=p48 lab=D1}
|
||||
C {iopin.sym} 1160 -1350 0 1 {name=p49 lab=vdd}
|
||||
C {iopin.sym} 1240 -1350 0 1 {name=p50 lab=vref}
|
||||
|
|
@ -252,3 +231,24 @@ C {lab_pin.sym} 2050 -470 0 0 {name=p81 sig_type=std_logic lab=gnd}
|
|||
C {lab_pin.sym} 2050 -280 0 0 {name=p82 sig_type=std_logic lab=gnd}
|
||||
C {lab_pin.sym} 2050 -190 0 0 {name=p83 sig_type=std_logic lab=gnd}
|
||||
C {lab_pin.sym} 2050 -140 0 0 {name=p84 sig_type=std_logic lab=gnd}
|
||||
C {T_gate.sym} 440 -1100 0 0 {name=x1}
|
||||
C {T_gate.sym} 440 -490 0 0 {name=x2}
|
||||
C {T_gate.sym} 440 -160 0 0 {name=x4}
|
||||
C {T_gate.sym} 1040 -170 0 0 {name=x5}
|
||||
C {T_gate.sym} 1620 -180 0 0 {name=x6}
|
||||
C {T_gate.sym} 2190 -190 0 0 {name=x8}
|
||||
C {T_gate.sym} 2190 -520 0 0 {name=x9}
|
||||
C {T_gate.sym} 1620 -510 0 0 {name=x11}
|
||||
C {T_gate.sym} 1610 -790 0 0 {name=x12}
|
||||
C {T_gate.sym} 1610 -1120 0 0 {name=x14}
|
||||
C {T_gate.sym} 1040 -1110 0 0 {name=x15}
|
||||
C {T_gate.sym} 1040 -780 0 0 {name=x17}
|
||||
C {T_gate.sym} 440 -770 0 0 {name=x18}
|
||||
C {T_gate.sym} 1040 -500 0 0 {name=x20}
|
||||
C {inverter.sym} 280 -320 0 0 {name=x3}
|
||||
C {inverter.sym} 280 -930 0 0 {name=x7}
|
||||
C {inverter.sym} 880 -940 0 0 {name=x10}
|
||||
C {inverter.sym} 1450 -950 0 0 {name=x13}
|
||||
C {inverter.sym} 880 -330 0 0 {name=x16}
|
||||
C {inverter.sym} 1460 -340 0 0 {name=x19}
|
||||
C {inverter.sym} 2030 -350 0 0 {name=x21}
|
||||
|
|
|
|||
|
|
@ -52,15 +52,14 @@ logx=0
|
|||
logy=0
|
||||
color=4
|
||||
node=clk_comp}
|
||||
N 1500 -1480 1500 -1420 {lab=vref}
|
||||
N 1260 -1480 1260 -1420 {lab=1}
|
||||
N 1290 -1480 1290 -1420 {lab=2}
|
||||
N 1320 -1480 1320 -1420 {lab=3}
|
||||
N 1350 -1480 1350 -1420 {lab=4}
|
||||
N 1380 -1480 1380 -1420 {lab=5}
|
||||
N 1410 -1480 1410 -1420 {lab=6}
|
||||
N 1440 -1480 1440 -1420 {lab=7}
|
||||
N 1470 -1480 1470 -1420 {lab=8}
|
||||
N 1480 -1480 1480 -1420 {lab=vref}
|
||||
N 1270 -1480 1270 -1420 {lab=1}
|
||||
N 1300 -1480 1300 -1420 {lab=2}
|
||||
N 1330 -1480 1330 -1420 {lab=3}
|
||||
N 1360 -1480 1360 -1420 {lab=4}
|
||||
N 1390 -1480 1390 -1420 {lab=5}
|
||||
N 1420 -1480 1420 -1420 {lab=6}
|
||||
N 1450 -1480 1450 -1420 {lab=7}
|
||||
N 1510 -1600 1550 -1600 {lab=vdd}
|
||||
N 1490 -1620 1490 -1600 {lab=GND}
|
||||
N 1490 -1620 1610 -1620 {lab=GND}
|
||||
|
|
@ -81,25 +80,21 @@ N 1350 -1730 1380 -1730 {lab=clk_comp}
|
|||
N 1350 -1730 1350 -1600 {lab=clk_comp}
|
||||
N 1320 -1730 1350 -1730 {lab=clk_comp}
|
||||
N 1320 -1730 1320 -1600 {lab=clk_comp}
|
||||
N 1290 -1730 1320 -1730 {lab=clk_comp}
|
||||
N 1290 -1730 1290 -1600 {lab=clk_comp}
|
||||
N 1260 -1730 1290 -1730 {lab=clk_comp}
|
||||
N 1260 -1730 1260 -1600 {lab=clk_comp}
|
||||
N 980 -1730 1260 -1730 {lab=clk_comp}
|
||||
N 1280 -1730 1280 -1600 {lab=clk_comp}
|
||||
N 1280 -1730 1320 -1730 {lab=clk_comp}
|
||||
N 980 -1730 1280 -1730 {lab=clk_comp}
|
||||
N 1190 -1360 1220 -1360 {lab=vdd}
|
||||
N 1540 -1360 1590 -1360 {lab=vo}
|
||||
C {devices/lab_pin.sym} 1550 -1600 2 0 {name=p12 sig_type=std_logic lab=vdd}
|
||||
C {devices/lab_pin.sym} 1500 -1440 2 0 {name=p8 sig_type=std_logic lab=vref}
|
||||
C {switch_array.sym} 1380 -1540 2 1 {name=x5}
|
||||
C {devices/lab_pin.sym} 1480 -1450 2 0 {name=p8 sig_type=std_logic lab=vref}
|
||||
C {gnd.sym} 1610 -1620 0 0 {name=l1 lab=GND}
|
||||
C {devices/lab_pin.sym} 1260 -1440 0 0 {name=p77 sig_type=std_logic lab=1}
|
||||
C {devices/lab_pin.sym} 1290 -1440 0 0 {name=p78 sig_type=std_logic lab=2}
|
||||
C {devices/lab_pin.sym} 1320 -1440 0 0 {name=p79 sig_type=std_logic lab=3}
|
||||
C {devices/lab_pin.sym} 1350 -1440 0 0 {name=p80 sig_type=std_logic lab=4}
|
||||
C {devices/lab_pin.sym} 1380 -1440 0 0 {name=p81 sig_type=std_logic lab=5}
|
||||
C {devices/lab_pin.sym} 1410 -1440 0 0 {name=p82 sig_type=std_logic lab=6}
|
||||
C {devices/lab_pin.sym} 1440 -1440 0 0 {name=p83 sig_type=std_logic lab=7}
|
||||
C {devices/lab_pin.sym} 1470 -1440 0 0 {name=p84 sig_type=std_logic lab=8}
|
||||
C {devices/lab_pin.sym} 1270 -1440 0 0 {name=p77 sig_type=std_logic lab=1}
|
||||
C {devices/lab_pin.sym} 1300 -1440 0 0 {name=p78 sig_type=std_logic lab=2}
|
||||
C {devices/lab_pin.sym} 1330 -1440 0 0 {name=p79 sig_type=std_logic lab=3}
|
||||
C {devices/lab_pin.sym} 1360 -1440 0 0 {name=p80 sig_type=std_logic lab=4}
|
||||
C {devices/lab_pin.sym} 1390 -1440 0 0 {name=p81 sig_type=std_logic lab=5}
|
||||
C {devices/lab_pin.sym} 1420 -1440 0 0 {name=p82 sig_type=std_logic lab=6}
|
||||
C {devices/lab_pin.sym} 1450 -1440 0 0 {name=p83 sig_type=std_logic lab=7}
|
||||
C {devices/lab_pin.sym} 980 -1730 2 0 {name=p24 sig_type=std_logic lab=clk_comp}
|
||||
C {devices/gnd.sym} 980 -1640 0 0 {name=l6 lab=GND}
|
||||
C {devices/vsource.sym} 980 -1680 0 0 {name=V1 value="dc 0 ac 0 PULSE(0 1.2 0 1n 1n 31.25n 62.5n)"}
|
||||
|
|
@ -124,7 +119,6 @@ tclcommand="xschem raw_read $netlist_dir/switch_array_tb.raw tran"
|
|||
C {devices/lab_pin.sym} 980 -1600 2 0 {name=p3 sig_type=std_logic lab=vdd}
|
||||
C {devices/gnd.sym} 980 -1510 0 0 {name=l4 lab=GND}
|
||||
C {devices/vsource.sym} 980 -1550 0 0 {name=V4 value=1.2}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/C-DAC/C-DAC.sym} 1370 -1360 2 1 {name=x3}
|
||||
C {devices/lab_pin.sym} 1590 -1360 2 0 {name=p4 sig_type=std_logic lab=vo}
|
||||
C {devices/code_shown.sym} 940 -1060 0 0 {name=MODEL1 only_toplevel=true
|
||||
format="tcleval( @value )"
|
||||
|
|
@ -132,3 +126,5 @@ value=".lib cornerMOSlv.lib mos_tt
|
|||
.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
|
||||
"}
|
||||
C {devices/lab_pin.sym} 1190 -1360 2 1 {name=p5 sig_type=std_logic lab=vdd}
|
||||
C {switch_array.sym} 1380 -1540 2 1 {name=x1}
|
||||
C {C-DAC.sym} 1370 -1360 2 1 {name=x2}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
# xschemrc - Custom configuration file for xschem
|
||||
# This file sources another xschemrc file from a known location
|
||||
|
||||
# Source the base configuration from a known location
|
||||
source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
|
||||
|
||||
# (Optional) Add any custom overrides or extensions below
|
||||
# set xschem_library_path /home/user/my_libs
|
||||
# set xschem_gui_font "Monospace 10"
|
||||
|
||||
#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
|
||||
###only if you dont have this setup already ###
|
||||
###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
|
||||
|
||||
|
||||
#### Add custom libraries (directories with .lib files)
|
||||
append XSCHEM_LIBRARY_PATH :../../part_2_digital_comps/T_gate/schematic/
|
||||
append XSCHEM_LIBRARY_PATH :../../part_2_digital_comps/bootstrap_switch/schematic/
|
||||
append XSCHEM_LIBRARY_PATH :../C-DAC/
|
||||
|
|
@ -213,7 +213,6 @@ let comp_diff = v(op)- v(om)
|
|||
set wr_singlescale
|
||||
set wr_vecnames
|
||||
wrdata bit_data.txt D0 D1 D2 D3 D4 D5 D6 D7 vin_diff dac_clk
|
||||
write SAR_ADC_tb.raw
|
||||
.endc
|
||||
"}
|
||||
C {devices/launcher.sym} 2072.5 -590 0 0 {name=h1
|
||||
|
|
@ -226,174 +225,9 @@ C {devices/lab_pin.sym} 1370 -1470 2 0 {name=p12 sig_type=std_logic lab=vdd}
|
|||
C {devices/lab_pin.sym} 265 -680 2 1 {name=p3 sig_type=std_logic lab=Op}
|
||||
C {devices/lab_pin.sym} 265 -660 2 1 {name=p13 sig_type=std_logic lab=vdd}
|
||||
C {devices/lab_pin.sym} 265 -640 2 1 {name=p14 sig_type=std_logic lab=Om}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -700 0 0 {name=A1
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -680 0 0 {name=A2
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -660 0 0 {name=A3
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -640 0 0 {name=A4
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/adc_bridge1.sym} 315 -620 0 0 {name=A5
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -870 0 0 {name=A7
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -850 0 0 {name=A8
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -830 0 0 {name=A9
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -810 0 0 {name=A10
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -790 0 0 {name=A11
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -770 0 0 {name=A12
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -750 0 0 {name=A13
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -730 0 0 {name=A14
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -710 0 0 {name=A15
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -690 0 0 {name=A16
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -670 0 0 {name=A17
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -650 0 0 {name=A18
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -630 0 0 {name=A19
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -610 0 0 {name=A20
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -590 0 0 {name=A21
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -570 0 0 {name=A22
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -550 0 0 {name=A23
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -530 0 0 {name=A24
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -510 0 0 {name=A25
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -490 0 0 {name=A26
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -470 0 0 {name=A27
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/dac_bridge1.sym} 645 -450 0 0 {name=A28
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_1_comparator/schematic/dynamic_comparator.sym} 1770 -1170 0 0 {name=x1}
|
||||
C {devices/lab_pin.sym} 1950 -1180 2 0 {name=p36 sig_type=std_logic lab=Op}
|
||||
C {devices/lab_pin.sym} 1950 -1160 2 0 {name=p37 sig_type=std_logic lab=Om}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/C-DAC/C-DAC.sym} 1190 -1110 0 0 {name=x2}
|
||||
C {devices/lab_pin.sym} 1570 -1170 2 1 {name=p5 sig_type=std_logic lab=bias}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array.sym} 1200 -930 0 0 {name=x4}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/switch_array/switch_array.sym} 1200 -1410 2 1 {name=x5}
|
||||
C {gnd.sym} 1430 -1490 0 0 {name=l1 lab=GND}
|
||||
C {devices/lab_pin.sym} 1370 -870 0 1 {name=p38 sig_type=std_logic lab=vdd}
|
||||
C {gnd.sym} 1430 -850 2 1 {name=l2 lab=GND}
|
||||
|
|
@ -425,8 +259,6 @@ C {devices/lab_pin.sym} 1005 -690 0 1 {name=p15 sig_type=std_logic lab=BN3}
|
|||
C {devices/lab_pin.sym} 1005 -670 0 1 {name=p16 sig_type=std_logic lab=BN4}
|
||||
C {devices/lab_pin.sym} 1005 -730 0 1 {name=p18 sig_type=std_logic lab=BN1}
|
||||
C {devices/lab_pin.sym} 1005 -630 0 1 {name=p19 sig_type=std_logic lab=BN6}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sym} 820 -1230 0 0 {name=x6}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/bootstrap_switch/schematic/bootstrap_switch.sym} 820 -1110 0 0 {name=x7}
|
||||
C {gnd.sym} 780 -1150 0 1 {name=l3 lab=GND}
|
||||
C {gnd.sym} 780 -1030 0 1 {name=l4 lab=GND}
|
||||
C {devices/lab_pin.sym} 840 -1140 2 0 {name=p20 sig_type=std_logic lab=vdd}
|
||||
|
|
@ -473,11 +305,6 @@ C {gnd.sym} 1940 -1050 0 1 {name=l5 lab=GND}
|
|||
C {gnd.sym} 1940 -1290 2 1 {name=l14 lab=GND}
|
||||
C {devices/lab_pin.sym} 1400 -1230 3 1 {name=p74 sig_type=std_logic lab=CDAC_v+}
|
||||
C {devices/lab_pin.sym} 1400 -1110 1 1 {name=p73 sig_type=std_logic lab=CDAC_v-}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_3_array_components/C-DAC/C-DAC.sym} 1190 -1230 2 1 {name=x3}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/algorithm/xschem/sar_logic.sym} 485 -660 0 0 {name=adut1
|
||||
dut=dut
|
||||
d_cosim_model= d_cosim
|
||||
model=./sar_logic.so}
|
||||
C {devices/lab_pin.sym} 700 -1230 2 1 {name=p25 sig_type=std_logic lab=vin_pos}
|
||||
C {devices/lab_pin.sym} 700 -1110 2 1 {name=p69 sig_type=std_logic lab=vin_neg}
|
||||
C {devices/lab_pin.sym} 260 -855 2 1 {name=p75 sig_type=std_logic lab=vin_pos}
|
||||
|
|
@ -494,7 +321,6 @@ C {devices/vsource.sym} 260 -930 0 1 {name=V4 value="dc 0 ac 0 SIN(0.6 0.3 12.7k
|
|||
C {devices/lab_pin.sym} 260 -700 2 1 {name=p27 sig_type=std_logic lab=clk_algo}
|
||||
C {devices/lab_pin.sym} 260 -980 2 1 {name=p8 sig_type=std_logic lab=vin_neg}
|
||||
C {devices/vsource.sym} 300 -1190 0 0 {name=V5 value="dc 0 ac 0 PULSE(0 1.2 0 10p 10p T_half T)"}
|
||||
C {/home/pedersen/projects/IHP-AnalogAcademy/modules/module_3_8_bit_SAR_ADC/part_2_digital_comps/nand_gate/schematic/nand_gate.sym} 1730 -1450 0 0 {name=x8}
|
||||
C {devices/lab_pin.sym} 1560 -1490 2 1 {name=p9 sig_type=std_logic lab=Op}
|
||||
C {devices/lab_pin.sym} 1560 -1430 2 1 {name=p11 sig_type=std_logic lab=Om}
|
||||
C {devices/lab_pin.sym} 1670 -1570 2 1 {name=p34 sig_type=std_logic lab=vdd}
|
||||
|
|
@ -506,3 +332,177 @@ value=20f
|
|||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {devices/lab_pin.sym} 1830 -1460 2 0 {name=p35 sig_type=std_logic lab=clk_algo}
|
||||
C {sar_logic.sym} 485 -660 0 0 {name=adut
|
||||
dut=dut
|
||||
d_cosim_model= d_cosim
|
||||
model=./sar_logic.so}
|
||||
C {adc_bridge1.sym} 315 -700 0 0 {name=A6
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {adc_bridge1.sym} 315 -680 0 0 {name=A1
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {adc_bridge1.sym} 315 -660 0 0 {name=A2
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {adc_bridge1.sym} 315 -640 0 0 {name=A3
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {adc_bridge1.sym} 315 -620 0 0 {name=A4
|
||||
adc=adc1
|
||||
adc_bridge_model=adc_bridge
|
||||
in_low=0.2
|
||||
in_high=0.8
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -870 0 0 {name=A5
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -850 0 0 {name=A7
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -830 0 0 {name=A8
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -810 0 0 {name=A9
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -790 0 0 {name=A10
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -770 0 0 {name=A11
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -750 0 0 {name=A12
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -730 0 0 {name=A13
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -710 0 0 {name=A14
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -690 0 0 {name=A15
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -670 0 0 {name=A16
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -650 0 0 {name=A17
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -630 0 0 {name=A18
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -610 0 0 {name=A19
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -590 0 0 {name=A20
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -570 0 0 {name=A21
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -550 0 0 {name=A22
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -530 0 0 {name=A23
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -510 0 0 {name=A24
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -490 0 0 {name=A25
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -470 0 0 {name=A26
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {dac_bridge1.sym} 645 -450 0 0 {name=A27
|
||||
dac=dac1
|
||||
dac_bridge_model=dac_bridge
|
||||
out_low=0
|
||||
out_high=1.2
|
||||
}
|
||||
C {switch_array.sym} 1200 -1410 2 1 {name=x4}
|
||||
C {C-DAC.sym} 1190 -1110 0 0 {name=x2}
|
||||
C {C-DAC.sym} 1190 -1230 2 1 {name=x3}
|
||||
C {switch_array.sym} 1200 -930 0 0 {name=x5}
|
||||
C {bootstrap_switch.sym} 820 -1230 0 0 {name=x6}
|
||||
C {bootstrap_switch.sym} 820 -1110 0 0 {name=x7}
|
||||
C {nand_gate.sym} 1730 -1450 0 0 {name=x1}
|
||||
C {dynamic_comparator.sym} 1770 -1170 0 0 {name=x8}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
# xschemrc - Custom configuration file for xschem
|
||||
# This file sources another xschemrc file from a known location
|
||||
|
||||
# Source the base configuration from a known location
|
||||
source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
|
||||
|
||||
# (Optional) Add any custom overrides or extensions below
|
||||
# set xschem_library_path /home/user/my_libs
|
||||
# set xschem_gui_font "Monospace 10"
|
||||
|
||||
#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
|
||||
###only if you dont have this setup already ###
|
||||
###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
|
||||
|
||||
|
||||
#### Add custom libraries (directories with .lib files)
|
||||
append XSCHEM_LIBRARY_PATH :../part_1_comparator/schematic/
|
||||
append XSCHEM_LIBRARY_PATH :../part_2_digital_comps/algorithm/xschem/
|
||||
append XSCHEM_LIBRARY_PATH :../part_2_digital_comps/bootstrap_switch/schematic/
|
||||
append XSCHEM_LIBRARY_PATH :../part_2_digital_comps/nand_gate/schematic/
|
||||
append XSCHEM_LIBRARY_PATH :../part_2_digital_comps/T_gate/schematic/
|
||||
append XSCHEM_LIBRARY_PATH :../part_3_array_components/C-DAC/
|
||||
append XSCHEM_LIBRARY_PATH :../part_3_array_components/switch_array/
|
||||
Loading…
Reference in New Issue