In this tutorial, we will guide you through the systematic process of laying out the bandgap reference circuit. This task is divided into two parts: the design of the two-stage OTA and the bandgap core, both of which were created in parts 1 and 2 of this series. The primary focus here is to transition the design from the schematic editor into KLayout for layout implementation, ensuring that pycells are correctly utilized in the layout process.
### Extracting Pycells from the Netlist and Performing LVS
Within part 3 of the tutorial, you will find the recommended setup for organizing your layout procedure. The `pycell_macro` folder contains the generator script we will use to create the layout. This script takes a netlist in the `.spice` format as input and processes it in batch mode. Here’s an example of how to use it for the two-stage OTA:
### Exporting the Netlist Correctly
Before starting the layout design, we must first export the netlist properly. To begin, launch the OTA design in **xschem** and navigate to the **Simulation** submenu. Within this menu, select the **LVS** option. Ensure that the **Use 'spiceprefix' attribute** checkbox is selected. Once this is done, click on **Netlist** to generate the corresponding simulation files.
Navigate to the simulation folder, which is located in the same directory as your schematic file. You should see a `.spice` file with the same name as the schematic. Open this file in your preferred text editor. The content will look like the following:
A netlist is essentially a list of components and their connections used for simulations. Here's a breakdown of the main elements:
- **Subcircuit Definition (`.subckt`)**: Defines the name of the circuit and its connections (e.g., `vdd`, `iout`, `v+`, etc.).
- **Device Definitions (`XM`, `XC`)**: These lines represent components (e.g., transistors and capacitors) and their connections, along with key parameters like width, length, and model.
- **Pins (`.iopin`)**: Specifies external connection points for the subcircuit.
- **End Markers (`.ends`, `.end`)**: Marks the beginning and end of the subcircuit and netlist.
### Creating the Device Gallery
With the netlist verified, we can now proceed to create the GDS file containing our layout. To achieve this, we will utilize the generator script located in the `pycell_macro` folder. We want to run it in batch mode. Here’s the general form for executing the script:
As we move into the layout phase, performing LVS (Layout vs. Schematic) checks is crucial to ensure that the layout matches the schematic design. Preparing the netlist in the correct format is a key step in this process.
- Note that the instance prefixes (e.g., `X`) have been removed, which is necessary for LVS.
- **Update the Layout in KLayout**:
- Open the layout in **KLayout**.
- Navigate to the **Cells** menu and rename the top cell (e.g., `gallery`) to match the top cell name in your netlist. For instance, rename it to `two_stage_OTA` in this case.
- **Run the LVS in KLayout**:
- Open the **SG13G2 PDK** menu and select **SG13G2 LVS Options**.
- Finally, navigate to the **LVS** option in the same menu to run the LVS check.
At this point you should see a lot of uncorrected LVS issues.
# Klayout video tutorial
The linked video provides a walkthrough on designing the input pair of an OTA for a bandgap reference and demonstrates how to complete a layout using open-source tools. While this is not a comprehensive,
end-to-end tutorial—such a deep dive would require far more time than is practical for a single video—it covers the essentials.
You’ll learn how to navigate KLayout effectively and establish a solid layout workflow, laying the foundation for more advanced design tasks.
