The simulation library allows you to explore different designs and understand the simulation setups, which will be covered in detail throughout the course. To get started, try opening dc_lv_nmos by selecting the instance and pressing e. This will open the schematic view.
From here, navigate to the "netlist" button in the top-right corner, then press "simulate." Your first schematic simulation in Xschem will now be complete. View the results by left-clicking the green arrow while holding down Ctrl. The output should look like this:
Analog design requires a solid foundation in analog electronics to ensure high-performance, robust designs. In this course, we will focus on the gm/Id methodology rather than traditional small-signal calculations using square-law models. This method uses model parameters to generate lookup tables, enabling a more data-driven approach to design. If you're interested in understanding the circuit design procedures in greater detail, each module includes Jupyter Notebook scripts as references for more advanced IC design using open-source tools.
Switch to the "Ngspice" branch and clone the repository to a destination of your choice. Follow the installation instructions in the README. To generate the lookup table, create a configuration file specifying parameters. Below is a sample configuration file to sweep the low-voltage devices, sg13_lv_nmos and sg13_lv_pmos, with relevant parameters:
This command will generate a .pkl file that serves as the lookup table. To test the table, navigate to the scripting folder in this module and open gmid_commonsource.ipynb.
Note: Ensure the paths to sg13g2_nmos_lv and sg13g2_pmos_lv are correctly referenced in your config file, and modify the LUT path in the script to point to the location of your lookup tables.
## Verifying gm/Id Design in Xschem (Optional)
To verify the design created using the lookup tables, start by identifying key parameters to validate, such as DC gain and the first pole. This requires creating a frequency analysis simulation to capture both characteristics. Begin by creating a new schematic in some specified folder:
the first thing we want to do is the instanciate our mosfets. In this example we make a current mirror for biasing our output transistor to the right operation. Therefore we will need to instanciate two MOSFETS. This is done by navigating to the insert symbol botton, with a nandgate as its icon. Or you can press shift+i. Here you want to click the IHP open pdk path, and click on "sg13g2_pr". Here you should select the "sg13_lv_nmos.sym", and press OK. Now you will place it and duplicate it by pressing it and clicking "c". Now you can press shift+f while toggeling the instance for flipping it and place it in a gate to gate configuration as shown in the image:
select each instance and press Q to change the widht and the length to the parameters found in the gmid script.
Now you should conncect the bulk of the devices to the sources with a wire, by pressing "w" and dragging the wire to its location. After this navigate to the symbol library, again by pressing and instanciate the following items:
modify each instance in the same way as the transistors so you also have the same values and labels. NOTE the Vin1 source has the following settings for value "value = AC 1". Next up we want to write the code for our simulation. Chose one of the code_shown blocks and press Q. In here change the name to NGSPICE and set only_toplevel to true. In the value section, insert the following code:
- .control ... .endc: This block defines a sequence of commands to control the simulation.
- op: Runs a DC operating point analysis, which calculates the steady-state (DC) node voltages and currents based on the current sources, voltage sources, and component values.
- ac dec 20 1 1e12: Runs an AC analysis with the following parameters:
- dec: Specifies a logarithmic frequency sweep (in decades).
- 20: Defines the number of points per decade.
- 1 and 1e12: Sets the frequency range from 1 Hz to 1 THz. This analysis evaluates the frequency response of the circuit over this range.
- save all: Instructs Ngspice to save all node voltages and branch currents during the simulation. This allows for detailed data analysis and access to all circuit variables.
- let Av = db(v(vout)): Defines a new variable Av to store the voltage gain (in decibels) at the node vout. Here:
- v(vout) retrieves the voltage at the vout node.
- db(...) converts this voltage to decibels (dB) for gain measurement.
- write output_file.raw: Saves all the collected data and defined variables (Av and phase) to a file named output_file.raw. This output file can be used for post-simulation analysis or plotting in external tools.
For the second code block we want to include the model for the transistors, which is done by filling the value parameter with the following:
As the last step before we can simulate we must set the netlisting to spice netlist. For this navigate to options-> Netlist Format/Symbol mode and choose Spice netlist. Now everything is setup and you can click netlist in the top right corner and afterwards Simulate. When this is done, a window should pop up, with a message: binary raw file "output_file.raw". Now write
```
show all
```
in the input to display the DC operating points, and here you can verify that the operating points is set as calculated in the gm/id script. If not you can tweek the current source for instance to get a more accurate ids of your output transistor. In order to see the outputs avaliable for plotting, you can write
