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luke / sbt
Scala 0 0
sbt, the interactive build tool
scala zinc sbt build-tool
Updated 2026-07-11 22:04:01 +02:00
luke / klayout
C++ 0 0
KLayout Main Sources
qt klayout gds2 eda
Updated 2026-07-11 21:56:02 +02:00
luke / yosys
C++ 0 0
Yosys Open SYnthesis Suite
Updated 2026-07-11 13:06:42 +02:00
luke / magic
C 0 0
Magic VLSI Layout Tool
Updated 2026-07-11 01:59:05 +02:00
luke / iverilog
C++ 0 0
Icarus Verilog
Updated 2026-07-10 19:43:38 +02:00
luke / verilator
SystemVerilog 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2026-07-10 15:34:51 +02:00
luke / OpenSTA
C++ 0 0
OpenSTA engine
Updated 2026-07-09 06:24:46 +02:00
luke / ngspice
C 0 0
Updated 2026-07-08 23:02:08 +02:00
luke / netgen
C 0 0
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-07-07 08:00:05 +02:00
luke / prjxray
Python 0 0
Documenting the Xilinx 7-series bit-stream format.
Updated 2026-07-04 21:36:18 +02:00
luke / abc
C 0 0
ABC: System for Sequential Logic Synthesis and Formal Verification
Updated 2026-07-02 13:04:37 +02:00
luke / openFPGALoader
C++ 0 0
Universal utility for programming FPGA
fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone
Updated 2026-07-02 09:19:08 +02:00
luke / OpenRAM
Python 0 0
An open-source static random access memory (SRAM) compiler.
netlists netgen magic sram gds python ngspice
Updated 2026-06-27 20:52:18 +02:00
luke / nextpnr
C++ 0 0
nextpnr portable FPGA place and route tool
Updated 2026-06-21 09:53:14 +02:00
luke / IHP-AnalogAcademy
Jupyter Notebook 0 0
Updated 2026-06-16 14:40:18 +02:00
luke / prjpeppercorn
Python 0 0
Project Peppercorn - GateMate FPGA Bitstream Documentation
Updated 2026-06-16 14:07:15 +02:00
luke / xschem
C 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-06-16 09:24:40 +02:00
luke / prjxray-db
Makefile 0 0
Project X-Ray Database: XC7 Series
Updated 2026-06-16 02:16:21 +02:00
luke / UberDDR3
Verilog 0 0
Opensource DDR3 Controller
fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3
Updated 2026-06-12 06:11:53 +02:00
luke / cxxopt
C++ 0 0
Lightweight C++ command line option parser
positional-arguments option-parser c-plus-plus
Updated 2026-06-03 09:57:48 +02:00