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luke / sbt
Scala 0 0
sbt, the interactive build tool
scala zinc sbt build-tool
Updated 2026-04-26 00:03:50 +02:00
luke / verilator
SystemVerilog 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2026-04-25 18:56:03 +02:00
luke / ngspice
C 0 0
Updated 2026-04-25 17:17:09 +02:00
luke / yosys
C++ 0 0
Yosys Open SYnthesis Suite
Updated 2026-04-25 10:41:31 +02:00
luke / magic
C 0 0
Magic VLSI Layout Tool
Updated 2026-04-24 17:21:15 +02:00
luke / xschem
C 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2026-04-24 13:52:52 +02:00
luke / prjxray-db
Makefile 0 0
Project X-Ray Database: XC7 Series
Updated 2026-04-24 07:18:59 +02:00
luke / OpenSTA
C++ 0 0
OpenSTA engine
Updated 2026-04-24 00:18:45 +02:00
luke / openFPGALoader
C++ 0 0
Universal utility for programming FPGA
fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone
Updated 2026-04-22 09:35:20 +02:00
luke / nextpnr
C++ 0 0
nextpnr portable FPGA place and route tool
Updated 2026-04-21 14:00:12 +02:00
luke / klayout
C++ 0 0
KLayout Main Sources
qt klayout gds2 eda
Updated 2026-04-20 22:55:27 +02:00
luke / OpenRAM
Python 0 0
An open-source static random access memory (SRAM) compiler.
netlists netgen magic sram gds python ngspice
Updated 2026-04-17 16:25:26 +02:00
luke / iverilog
C++ 0 0
Icarus Verilog
Updated 2026-04-15 17:51:17 +02:00
luke / prjpeppercorn
Python 0 0
Project Peppercorn - GateMate FPGA Bitstream Documentation
Updated 2026-04-07 13:36:29 +02:00
luke / netgen
C 0 0
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2026-04-04 08:00:02 +02:00
luke / manta
Python 0 0
A configurable and approachable tool for FPGA debugging and rapid prototyping.
fpga verilog icestorm icestick debug xilinx
Updated 2026-03-29 05:44:03 +02:00
luke / sv2v
Haskell 0 0
SystemVerilog to Verilog conversion
verilog yosys systemverilog conversion
Updated 2026-03-27 23:46:29 +01:00
luke / prjxray
Python 0 0
Documenting the Xilinx 7-series bit-stream format.
Updated 2026-03-24 17:02:55 +01:00
luke / IHP-AnalogAcademy
Jupyter Notebook 0 0
Updated 2026-02-17 16:08:52 +01:00
luke / UberDDR3
Verilog 0 0
Opensource DDR3 Controller
fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3
Updated 2026-01-18 05:25:34 +01:00