VLSIDAOpenRAM

sram_8_128_scn4m_subm.html

Compiled at: 2020-06-24

DRC errors: skipped

LVS errors: skipped

Git commit id: 8166adc512f36a28a6334c995999ac60a5fe5388

Ports and Configuration

TypeValue
WORD_SIZE8
NUM_WORDS128
NUM_BANKS1
NUM_RW_PORTS1
NUM_R_PORTS0
NUM_W_PORTS0
Area (µm2)0

Operating Conditions

ParameterMinTypMaxUnits
Power supply (VDD) range5.05.05.0Volts
Operating Temperature252525Celsius
Operating Frequency (F)2227MHz

Timing Data

Using analytical model: results may not be precise

ParameterMinMaxUnits
din0[7:0] setup rising0.0090.009ns
din0[7:0] setup falling0.0090.009ns
din0[7:0] hold rising0.0010.001ns
din0[7:0] hold falling0.0010.001ns
dout0[7:0] cell rise1.9382.467ns
dout0[7:0] cell fall2.1532.243ns
dout0[7:0] rise transition0.0060.015ns
dout0[7:0] fall transition0.0060.015ns
csb0 setup rising0.0090.009ns
csb0 setup falling0.0090.009ns
csb0 hold rising0.0010.001ns
csb0 hold falling0.0010.001ns
addr0[6:0] setup rising0.0090.009ns
addr0[6:0] setup falling0.0090.009ns
addr0[6:0] hold rising0.0010.001ns
addr0[6:0] hold falling0.0010.001ns
web0 setup rising0.0090.009ns
web0 setup falling0.0090.009ns
web0 hold rising0.0010.001ns
web0 hold falling0.0010.001ns

Power Data

PinsModePowerUnits
!csb0 & clk0 & !web0Read Rising6.1909mW
!csb0 & clk0 & !web0Read Falling6.1909mW
!csb0 & !clk0 & web0Write Rising6.1909mW
!csb0 & !clk0 & web0Write Falling6.1909mW
csb0leakage0.001282mW

Characterization Corners

Transistor TypePower SupplyTemperatureCorner Name
TT5.025_TT_5p0V_25C.lib
FF5.025_FF_5p0V_25C.lib
SS5.025_SS_5p0V_25C.lib

Deliverables

TypeDescriptionLink
.htmlThis datasheetsram_8_128_scn4m_subm.html
.libSynthesis modelssram_8_128_scn4m_subm_TT_5p0V_25C.lib
.libSynthesis modelssram_8_128_scn4m_subm_FF_5p0V_25C.lib
.libSynthesis modelssram_8_128_scn4m_subm_SS_5p0V_25C.lib
.logOpenRAM compile logsram_8_128_scn4m_subm.log
.pyOpenRAM configuration filesram_8_128_scn4m_subm.py
.spSPICE netlistssram_8_128_scn4m_subm.sp
.vVerilog simulation modelssram_8_128_scn4m_subm.v